Gate structure cut after formation of epitaxial active regions

Patent metadata

Field	Value
Publication number	US-9633906-B2
Application number	US-201414162904-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a semiconductor material portion located on a substrate and extending along a lengthwise direction;
a gate structure overlying a portion of said semiconductor material portion;
a pair of gate spacer portions contacting widthwise sidewalls of said gate structure and laterally spaced from each other by said gate structure along said lengthwise direction;
a dielectric liner contacting lengthwise sidewalls of said gate spacer portions and lengthwise sidewalls of said gate structure and laterally surrounding said semiconductor material portion, wherein said dielectric liner contacting said lengthwise sidewalls of said gate spacer portions has a topmost surface that is coplanar with a topmost surface of said gate spacer portions;
a pair of epitaxial active regions located on a topmost surface and sidewall surfaces of said semiconductor material portion; and
a metal semiconductor alloy region having a topmost surface that is located beneath said topmost surface of said gate spacer portions and contacting a topmost surface of one of said pair of epitaxial active regions and including a periphery laterally bounded by a periphery of an opening within said dielectric liner, wherein said dielectric liner contacting said lengthwise sidewalls of said gate spacer portions has a sidewall that directly contacts a sidewall of said metal semiconductor alloy region and a bottommost surface that is located directly on a portion of said topmost surface of one of said epitaxial active regions.

2. The semiconductor structure of claim 1 , wherein two of said lengthwise sidewalls of said pair of gate spacer portions and one of said lengthwise sidewalls of said gate structure are within a vertical plane.

3. The semiconductor structure of claim 2 , wherein sidewall surfaces of said pair of epitaxial active regions are within said vertical plane.

4. The semiconductor structure of claim 3 , wherein said pair of epitaxial active regions further includes additional sidewall surfaces located within another vertical plane that is more distal from a center of mass of said semiconductor material portion than said vertical plane.

5. The semiconductor structure of claim 1 , wherein said gate structure and said pair of gate spacer portions extend by a same lateral dimension in a horizontal direction within said widthwise sidewalls of said gate structure.

6. The semiconductor structure of claim 1 , wherein each of said pair of gate spacer portions contacts a top surface and sidewall surfaces of said semiconductor material portion.

7. The semiconductor structure of claim 1 , wherein said dielectric liner includes at least an opening around said gate structure, two openings overlying end portions of said semiconductor material portion, and an opening to a portion of the topmost surface of said epitaxial active regions.

8. The semiconductor structure of claim 1 , wherein each of said pair of epitaxial active regions includes:
a first widthwise sidewall in contact with a lower portion of one of said widthwise sidewalls of said gate spacer portions; and
a second widthwise sidewall in contact with an inner sidewall of said dielectric liner.

9. The semiconductor structure of claim 1 , wherein said bottommost surface of said dielectric liner is located above a bottommost surface of said gate spacer portions.

10. The semiconductor structure of claim 9 , wherein a lower portion of said lengthwise sidewalls of said gate spacer portions are void of said dielectric liner.

Assignees

• IBM
• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Cai Xiuyu
• Cheng Kangguo
• Faltermeier Johnathan E
• Khakifirooz Ali
• Standaert Theodorus E
• Xie Ruilong

Classifications

• H10P50/283

  by chemical means · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic