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System and method to inhibit erasing of portion of sector of split gate flash memory cells
US9633735B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9633735-B2 |
| Application number | US-201414486687-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2014 |
| Priority date | Jul 22, 2014 |
| Publication date | Apr 25, 2017 |
| Grant date | Apr 25, 2017 |
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- Title
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Abstract
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A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of erasing a portion of a sector of a flash memory system, the sector comprising a first row of flash memory cells and a second row of flash memory cells, wherein the first row and second row share an erase gate, comprising: applying a first non-zero bias voltage to a control gate for the first row, wherein the first non-zero bias voltage is around 9 volts; applying a second non-zero bias voltage to a control gate for the second row, wherein the second non-zero bias voltage is around −9 volts; applying a third non-zero bias voltage to a word line for the second row, wherein the third non-zero bias voltage is within the range of 0.8 to 5 volts; and applying a signal to the erase gate to erase the first row while not erasing the second row. 2. The method of claim 1 , wherein the first row of flash memory cells and the second row of flash memory cells each comprise split gate flash memory cells.
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Classifications
in voltage or current generators · CPC title
comprising cells containing a merged floating gate and select transistor · CPC title
Programming voltage switching circuits · CPC title
- G11C16/14Primary
Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title
with adaption or trimming of parameters · CPC title
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- What does patent US9633735B2 cover?
- A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.
- Who is the assignee on this patent?
- Silicon Storage Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/14. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).