Sequential erase for tuning the program state of non-volatile memory cells
US-2025285684-A1 · Sep 11, 2025 · US
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Tkachev Yuri patents
Tkachev Yuri is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Tkachev Yuri |
| Total patents | 21 |
| First publication | Feb 5, 2015 |
| Latest publication | Sep 11, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Programmable logic block comprising flash memory array to store configuration data for programmable logic
US-2025208774-A1 · Jun 26, 2025 · US
Low voltage resistive random access memory (rram) cells and method of formation
US-2025185523-A1 · Jun 5, 2025 · US
Semiconductor device with communication ring
US-2024274591-A1 · Aug 15, 2024 · US
Method of determining defective die containing non-volatile memory cells
US-12020762-B2 · Jun 25, 2024 · US
Method of Determining Defective Die Containing Non-volatile Memory Cells
US-2023101585-A1 · Mar 30, 2023 · US
Ultra-precise tuning of neural memory cells
US-2022336020-A1 · Oct 20, 2022 · US
Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network
US-11393535-B2 · Jul 19, 2022 · US
Method of forming split gate memory cells with thinned side edge tunnel oxide
US-11362218-B2 · Jun 14, 2022 · US
Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide
US-2021399127-A1 · Dec 23, 2021 · US
Recent patents
Latest publications not already listed above.
Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network
US-2021264983-A1 · Aug 26, 2021 · US
Method of forming split gate memory cells with thinned tunnel oxide
US-11018147-B1 · May 25, 2021 · US
Method of programming a split-gate flash memory cell with erase gate
US-10714489-B2 · Jul 14, 2020 · US
Method Of Programming A Split-Gate Flash Memory Cell With Erase Gate
US-2020066738-A1 · Feb 27, 2020 · US
System and method to inhibit erasing of portion of sector of split gate flash memory cells
US-9633735-B2 · Apr 25, 2017 · US
Split-gate memory cell with depletion-mode floating gate channel, and method of making same
US-9466732-B2 · Oct 11, 2016 · US
Low leakage, low threshold voltage, split-gate flash cell operation
US-9275748-B2 · Mar 1, 2016 · US
System And Method To Inhibit Erasing Of Portion Of Sector Of Split Gate Flash Memory Cells
US-2016027517-A1 · Jan 28, 2016 · US
Method of operating a split gate flash memory cell with coupling gate
US-9245638-B2 · Jan 26, 2016 · US
Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same
US-9123822-B2 · Sep 1, 2015 · US
Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same
US-2015035040-A1 · Feb 5, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Silicon Storage Tech Inc | 21 |
| Tkachev Yuri | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B41/30 | 9 |
| G11C16/14 | 8 |
| H10D64/035 | 7 |
| H10D30/6892 | 7 |
| H01L27/11521 | 6 |