Method for deriving characteristic values of MOS transistor

Patent metadata

Field	Value
Publication number	US-9632115-B2
Application number	US-201313894021-A
Country	US
Kind code	B2
Filing date	May 14, 2013
Priority date	May 14, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method for deriving characteristic values of a MOS transistor is described. A set of η k values is provided. A set of V Bi values (i=1 to M, M≧3) is provided. A set of RSD i,j (i=1 to M−1, j=i+1 to M) values each under a pair of V Bi and V Bj , or a set of V tq _ q,j (q is one of 1 to M, j is 1 to M excluding q) values under V Bq is derived for each η k , with an iteration method. The η k value making the set of RSD i,j values or V tq _ q,j values closest to each other is determined as an accurate η k value. The mean value of RSD i,j at the accurate η k value is calculated as an accurate RSD value.

First claim

What is claimed is:

1. A method for deriving characteristic values of a MOS transistor, wherein the MOS transistor comprises a substrate, a gate, a channel region, a source and a drain, a threshold voltage of the channel region is V t , a voltage applied to the substrate is V B , a voltage applied to the gate is V G , a voltage across the source and the drain is V DS , a voltage across the gate and the source is V GS , a V GS making the MOS transistor operate in a constant-mobility region is V GS _ c , a current from the drain to the source is I DS , and a sum of a resistance R D of the drain and a resistance R S of the source is RSD, the method comprising:
a) applying different V B1 and V B2 , respectively, to the substrate;
b) measuring I DS1 and I DS2 that correspond to V B1 and V B2 , respectively;
c) giving respective initial values of V t1 and V t2 , wherein V t1 corresponds to V B1 and V t2 corresponds to V B2 ;
d) calculating RSD with a given η value, V t1 and V t2 by an equation of

R
⁢

⁢
S
⁢

⁢
D

=

(

V
GS_c

+

(

η
-
1

)

⁢

V

t
⁢

⁢
1

-

η
⁢

⁢

V

t
⁢

⁢
2

-

0.5
⁢

V
DS

I

DS
⁢

⁢
2

-

V
GS_c

-

V

t
⁢

⁢
1

-

0.5
⁢

V
DS

I

DS
⁢

⁢
1

)

×

V
DS

η
×

(

V

t
⁢

⁢
1

-

V

t
⁢

⁢
2

)

;

e) applying a series of V G 's respectively to the gate while the voltage applied to the substrate is fixed at V B1 , calculating a corresponding series of V GS 's from the series of V G 's and measuring a corresponding series of I DS1 's to plot a plot of V GS vs. I DS1 _ exclude _ RSD to derive V GS _ a1 , and applying a series of V G 's respectively to the gate while the voltage applied to the substrate is fixed at V B2 , calculating a corresponding series of V GS 's from the series of V G 's and measuring a corresponding series of I DS2 's to plot a plot of V GS vs. I DS2 _ exclude _ RSD to derive V GS _ a2 , wherein I DS1 _ exclude _ RSD and I DS2 _ exclude _ RSD are calculated by equations of

I

DS
⁢

⁢
1
⁢
_exclude
⁢
_RSD

=

I

DS
⁢

⁢

Assignees

• United Microelectronics Corp

Inventors

• Wu Yi-Ting
• Huang Cheng-Tung
• Lee Tsung-Han
• Ye Yi-Han

Classifications

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R19/0084 Primary

  Measuring voltage only · CPC title