Digital equalizer adaptation using on-die instrument

Patent metadata

Field	Value
Publication number	US-9628304-B2
Application number	US-201615194325-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Mar 14, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.

First claim

What is claimed is:

1. A method for detecting horizontal bounds of an envelope of serial digital data in a communications system, the method comprising:
setting a first voltage to a first reference voltage;
setting a second voltage to a second reference voltage smaller than the first reference voltage;
performing a horizontal phase sweep test on the serial digital data wherein the horizontal phase sweep test includes performing a horizontal phase sweep of the serial digital data between the first voltage and the second voltage and identifying whether a threshold rate of logical symbols is detected over the course of the horizontal sweep;
when the horizontal phase sweep test fails, decreasing the first voltage, increasing the second voltage, and repeating the horizontal phase sweep; and
when the horizontal phase sweep test succeeds, setting an upper envelope voltage to the first voltage and a lower envelope voltage to the second voltage.

2. The method of claim 1 , wherein performing the horizontal phase sweep test comprises providing an output of the horizontal phase sweep test to a bit error checker to identify whether the threshold rate of logical symbols is detected.

3. The method of claim 1 , wherein identifying whether the threshold rate of logical symbols is detected over the course of the horizontal phase sweep comprises comparing a number of logical symbols detected to a defined threshold number of logical symbols.

4. The method of claim 3 , wherein the logical symbols comprise a logical 0 or a logical 1 or both.

5. The method of claim 1 , wherein performing the horizontal phase sweep test comprises performing the horizontal phase sweep, wherein the horizontal phase sweep comprises stepping through phases of the serial data signal using a phase interpolator and sampling a resulting output by a sampler.

6. The method of claim 5 wherein the phases are stepped through at defined steps.

7. The method of claim 1 , wherein the first reference voltage is the maximum voltage rail of a communications system that receives the serial digital signal and the second reference voltage is the minimum voltage rail of the communications system.

8. The method of claim 1 comprising identifying a horizontal eye diagram size in which the first voltage represents an upper envelope voltage and the second voltage represents a lower envelope voltage of the horizontal eye diagram of the serial data signal.

9. A communication system comprising:
a receiver that receives an input signal and outputs an output signal;
envelope detection circuitry configured to:
receive the output signal of the receiver;
set a first voltage to a first reference voltage;
set a second voltage to a second reference voltage smaller than the first reference voltage;
perform a horizontal phase sweep test on the output signal of the receiver between the first voltage and the second voltage;
when the horizontal phase sweep test fails, decrease the first voltage, increase the second voltage, and repeat the horizontal phase sweep test; and
when the horizontal phase sweep test passes, identify an upper envelope voltage and a lower envelope voltage based on the first voltage and the second voltage.

10. The communication system of claim 9 , comprising an on-die instrument that identifies an eye opening size of the output signal based at least in part on the upper envelope voltage and on the lower envelope voltage.

11. The communication system of claim 10 , wherein the on-die instrument determines an equalization state of the output signal based on a comparison between the eye opening size and a predetermined eye opening size, wherein the equalization state is under-equalized, over-equalized, or adequately equalized.

12. The communication system of claim 11 , wherein an AC gain of the receiver, a DC gain of the receiver, or both are adjusted by the on-die instrument based on the equalization state of the output signal.

13. The communication system of claim 9 , wherein the input signal comprises a serial digital data signal.

14. Envelope detector circuitry comprising:
an on-die instrument (ODI) that performs horizontal phase sweeping on serial digital data between a first voltage and a second voltage smaller than the first voltage to produce sweeping data;
digital circuitry that performs a test of the sweeping data; and
a digital adaptation block configured to:
upon determining that the sweeping data failed the test, decreasing the first voltage and increasing the second voltage; and
upon determining that the sweeping data passed the test, setting the first voltage as an upper envelope voltage and setting the second voltage as a lower envelope voltage.

15. The envelope detector circuitry of claim 14 , wherein the digital circuitry that performs the test comprises a bit error checker.

16. The envelope detector circuitry of claim 14 , wherein the test of the sweeping data comprises determining if a combination of logical symbols has been found.

17. The envelope detector circuitry of claim 14 , wherein an initial value for the first voltage is a maximum voltage rail of the digital circuitry and the initial value for the second voltage is a minimum voltage rail of the digital circuitry.

18. The envelope detector circuitry of claim 14 , wherein the digital adaptation block adjusts a reference bit of the ODI upon determining that the sweeping data passed the test.

19. The envelope detector circuity of claim 14 , wherein the ODI determines an equalization state of the serial digital data based on a comparison between the eye opening of the serial digital data and a predetermined eye opening size, wherein the equalization state is under-equalized, over-equalized, or adequately equalized, and the eye opening is identified between the upper envelope voltage and the lower envelope voltage.

20. The envelope detector circuitry of claim 19 , wherein the determination of the equalization state by the ODI is based on the test of the sweeping data.

Assignees

• Altera Corp

Inventors

• Hoang Tim Tri
• Nguyen Nam V

Classifications

• H04L5/006

  Quality of the received signal, e.g. BER, SNR, water filling · CPC title

• H04L25/03

  Shaping networks in transmitter or receiver, e.g. adaptive shaping networks · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03019

  adaptive, i.e. capable of adjustment during data reception · CPC title

• H04B1/16

  Circuits · CPC title