Supply voltage tracking clock generator in adaptive clock distribution systems

Patent metadata

Field	Value
Publication number	US-9628089-B1
Application number	US-201615192996-A
Country	US
Kind code	B1
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An adaptive clock distribution (ACD) system with a voltage tracking clock generator (VTCG) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit, to generate a TLD clock by adding a preselected delay to a root clock, and a voltage droop detector for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector selects the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.

First claim

What is claimed is:

1. An adaptive clock distribution (ACD) system comprising:
a tunable-length delay (TLD) circuit configured to add a preselected delay to a root clock, to generate a TLD clock;
a voltage droop detector configured to detect a voltage droop in a supply voltage; and
a voltage tracking clock generator (VTCG) configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop; and
a clock selector configured to select the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.

2. The ACD system of claim 1 , further comprising a synchronizer and an adaptive control unit (ACU), wherein the voltage droop detector is configured to generate an error signal when the voltage droop is detected, and wherein the synchronizer is configured to synchronize the error signal to the TLD clock to generate a synchronized error and provide the synchronized error to the ACU and the VTCG.

3. The ACD system of claim 2 , wherein the VTCG is configured to provide a control to the clock selector to select the VTCG clock as the ACD clock based on the synchronized error.

4. The ACD system of claim 2 , wherein the ACU is configured to enable the VTCG to generate the VTCG clock based on the synchronized error.

5. The ACD system of claim 2 , wherein the voltage droop detector is configured to generate the error signal if a timing margin is negative, wherein the timing margin is a difference between a clock period of the root clock and a time delay of a tunable delay path, wherein the time delay of the tunable delay path increases during the voltage droop.

6. The ACD system of claim 1 , wherein the two or more values of the frequency of the VTCG clock during the voltage droop are less than a frequency of the TLD clock.

7. The ACD system of claim 1 , wherein the root clock is generated by a phase-locked loop (PLL).

8. The ACD system of claim 1 , wherein the VTCG comprises a ring oscillator, wherein a frequency of the VTCG clock is based on a delay of the ring oscillator, and wherein the delay of the ring oscillator is based on the supply voltage.

9. The ACD system of claim 8 , wherein the delay of the ring oscillator is adjusted based on delays through selectable numbers of one or more of: one or more coarse-grained delay elements or one or more fine-grained delay elements.

10. The ACD system of claim 1 , further comprising a calibrator configured to match the frequency of the VTCG clock to a frequency of the root clock.

11. The ACD system of claim 10 , wherein the calibrator comprises a set of flip-flops configured to convert a clock period into a thermometric code.

12. The ACD system of claim 11 , wherein the calibrator is configured to match a thermometric code of a clock period of the VTCG clock to a thermometric code of a clock period of the root clock.

13. A method of operating an adaptive clock distribution (ACD) system, the method comprising:
adding a tunable-length delay (TLD) to a root clock, to generate a TLD clock;
detecting a voltage droop in a supply voltage;
generating a voltage tracking clock generator (VTCG) clock with a frequency finely tuned to two or more values to correspond to a magnitude of the supply voltage during the voltage droop; and
selecting as an ACD clock to be provided to an electronic circuit, the VTCG clock during the voltage droop and the TLD clock when there is no voltage droop detected.

14. The method of claim 13 , comprising:
generating an error signal when the voltage droop is detected;
synchronizing the error signal to the TLD clock to generate a synchronized error; and
selecting the ACD clock and enabling the VTCG based on the synchronized error.

15. The method of claim 14 , comprising generating the error signal if a timing margin is negative, wherein the timing margin is a difference between a clock period of the root clock and a time delay of a tunable delay path, wherein the time delay of the tunable delay path increases during the voltage droop.

16. The method of claim 13 , comprising generating the root clock from a phase-locked loop (PLL).

17. The method of claim 13 comprising generating the VTCG clock from a ring oscillator wherein a delay of the ring oscillator is based on the supply voltage.

18. The method of claim 17 , comprising adjusting the delay of the ring oscillator based on selecting delays through one or more of: one or more coarse-grained delay elements or one or more fine-grained delay elements.

19. The method of claim 13 , further comprising calibrating the frequency of the VTCG clock to match a frequency of the root clock.

20. The method of claim 19 , comprising matching a thermometric code of a clock period of the VTCG clock to a thermometric code of a clock period of the root clock.

21. An apparatus comprising:
means for adding a tunable-length delay (TLD) to a root clock to generate a TLD clock;
means for detecting a voltage droop in a supply voltage;
means for generating a voltage tracking clock generator (VTCG) clock with a frequency finely tuned to two or more values to correspond to a magnitude of the supply voltage during the voltage droop; and
means for selecting as a clock to be provided to an electronic circuit, the VTCG clock during the voltage droop and the TLD clock when there is no voltage droop detected.

22. The apparatus of claim 21 , further comprising:
means for generating an error signal when the voltage droop is detected;
means for synchronizing the error signal to the TLD clock to generate a synchronized error; and
means for selecting the clock and enabling the VTCG based on the synchronized.

23. The apparatus of claim 22 , further comprising means for generating the error signal if a timing margin is negative, wherein the timing margin is a difference between a clock period of the root clock and a time delay of a tunable delay path, wherein the time delay of the tunable delay path increases during the voltage droop.

24. The apparatus of claim 21 , further comprising means for generating the root clock from a phase-locked loop (PLL).

25. The apparatus of claim 21 , wherein the means for generating the VTCG clock comprises means for selecting delays through one or more of: one or more coarse-grained delay elements or one or more fine-grained delay elements.

26. The apparatus of claim 25 , further comprising means for calibrating the frequency of the VTCG clock to match a frequency of the root clock.

27. The apparatus of claim 26 , comprising means for matching a thermometric code of a clock period of the VTCG clock to a thermometric code of a clock period of the root clock.

Assignees

• Qualcomm Inc

Inventors

• Jain Palkesh
• Bowman Keith Alan
• Bansal Virendra

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title