Semiconductor device including a stack having a sidewall with recessed and protruding portions

Patent metadata

Field	Value
Publication number	US-9627396-B2
Application number	US-201514724952-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 30, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a stack on the substrate, the stack including gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, the gate electrodes and the insulating layers extending in a first direction parallel to a top surface of the substrate;
a first row of channel structures penetrating the stack, the channel structures in the first row being arranged spaced apart from each other in the first direction; and
a second row of channel structures penetrating the stack, the channel structures in the second row being arranged spaced apart from each other in the first direction,
the stack including a first sidewall extending in the first direction and a second sidewall opposite the first sidewall, the first and second rows of the channel structures between the first and second sidewalls,

the first sidewall including first recessed portions and first protruding portions,
each of the first protruding portions being defined by an adjacent pair of the first recessed portions,
each of the first recessed portions recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row,
each of the first recessed portions recessed beyond a virtual line connecting outermost points of the channel structures of the first row, when viewed in a plan view, and
each of the outermost points facing each of the first protruding portions, when viewed in a plan view.

2. The semiconductor device of claim 1 , wherein the first recessed portions are extended from a top of the stack to a bottom of the stack.

3. The semiconductor device of claim 1 ,
the first and second rows are spaced apart from each other in a second direction crossing the first direction,
the second sidewall includes second recessed portions and second protruding portions, each of the second protruding portions being defined by an adjacent pair of the second recessed portions, and
each of the second recessed portions recessed toward a second region between an adjacent pair of the channel structures of the second row.

4. The semiconductor device of claim 3 , wherein the channel structures of the first row are not overlapped with the channel structures of the second row in the second direction.

5. The semiconductor device of claim 3 , further comprising:
third and fourth rows of channel structures penetrating the stack, wherein
the third and fourth rows of channel structures are provided between the first and second rows of channel structures, and
the channel structures of each of the third and fourth rows are arranged spaced apart from each other in the first direction.

6. The semiconductor device of claim 5 , wherein
each of the channel structures of the first row overlaps with a corresponding one of the channel structures of the fourth row in the second direction,
each of the channel structures of the second row overlaps with a corresponding one of the channel structures of the third row in the second direction, and
the channel structures of the first row are not overlapped with the channel structures of the second row in the second direction.

7. The semiconductor device of claim 1 , wherein each of the first protruding portions has one of a triangular shape, a trapezoidal shape, and a semi-circular shape.

8. The semiconductor device of claim 1 , wherein
the first sidewall includes first and second straight lines that have first and second lengths, respectively,
the first and second straight lines meet each other at an angle θ ranging from −45° to 45°,
the second length is shorter than a distance obtained by dividing the first length by cos θ,
the first length is a distance from a center of each channel structure of the first row to an end of a corresponding one of the first protruding portions adjacent thereto, and
the second length is a distance from the center of each channel structure of the first row to a point of a side surface of the corresponding one of the first protruding portions.

9. The semiconductor device of claim 1 , further comprising:
vertical insulators between the stack and the first and second rows of channel structures,
wherein each of the vertical insulators includes a charge storing layer.

10. The semiconductor device of claim 1 , wherein the gate electrodes fill gap regions between the insulating layers.

11. A semiconductor device, comprising:
a substrate;
a stack including gate electrodes and insulating layers alternately stacked on top of each other on the substrate; and
a plurality of channel structures that are spaced apart from each other and extend vertically through the stack,
the gate electrodes and insulating layers defining a first row of channel holes that are spaced apart from each other in a first direction that crosses a second direction and a second row of channel holes that are spaced apart from each other in the first direction,
the gate electrodes and the insulating layer extending in the first direction,
the stack including a first sidewall extending over the substrate in a third direction that crosses the first and second directions, and a second sidewall opposite the first sidewall,
the first sidewall including a plurality of first recessed portions and a plurality of first protruding portions,
a width of the first protruding portions measured in the first direction decreasing as the first protruding portions protrude outward in the second direction away from the first row of the channel holes,
the plurality of channel structures including a first row of channel structures in the first row of channel holes and a second row of channel structures in the second row of channel holes, and
the first and second rows of the channel structures between the first and second sidewalls,
each of the first recessed portions recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row,
each of the first recessed portions recessed beyond a virtual line connecting outermost points of the channel structures of the first row, when viewed in a plan view, and
each of the outermost points facing each of the first protruding portions when viewed in a plan view.

12. The semiconductor device of claim 11 , wherein each of the first protruding portions has one of a triangular shape, a trapezoidal shape, and a semi-circular shape.

13. The semiconductor device of claim 11 , further comprising:
vertical insulators between the gate electrodes and the plurality of channel structures,
wherein each of the vertical insulators includes a charge storing layer.

14. The semiconductor device of claim 11 , wherein
the gate electrodes and insulating layers define a second row of channel holes that are spaced apart from each other in the first direction,
the first row of channel holes and the second channel holes are spaced apart from each other in the second direction and offset in the first direction such that the channel holes in the first row and the second row are arranged in a zig zag pattern,
the plurality of channel structures including a second row of channel structures in the second row of channel holes,
the second sidewall includes a plurality of second protruding portions,
a width of the second protruding portions measured in the first direction decreases as the second protruding portions protrude outward in the second direction away from the second row of the channel holes,
the first protruding portions are be arranged side-by-side with each other in the first direction along the first sidewall, and
the second protruding portions may be a

Assignees

• Son Byoungkeun
• Shin Yoocheol
• Lee Changhyun
• Kim Hyunjung
• Hyun Chung-Il
• Samsung Electronics Co Ltd

Inventors

• Son Byoungkeun
• Shin Yoocheol
• Lee Changhyun
• Kim Hyunjung
• Hyun Chung-Il

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic