Method for forming alignment marks and structure of same

Patent metadata

Field	Value
Publication number	US-9627326-B2
Application number	US-201615165834-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Mar 10, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

First claim

What is claimed is:

1. A method for forming alignment marks, the method comprising:
providing a substrate;
forming a first plurality of doped regions in a pixel region of the substrate;
forming a second plurality of doped regions in a frame cell region of the substrate; and
recessing the second plurality of doped regions, thereby forming a plurality of alignment marks.

2. The method of claim 1 , wherein the pixel region and the frame cell region are of a non-shallow trench isolation (non-STI) design.

3. The method of claim 1 , wherein the plurality of alignment marks comprises one or more zero layer alignment marks.

4. The method of claim 1 , wherein the plurality of alignment marks comprises one or more active area layer alignment marks.

5. The method of claim 4 , wherein the plurality of alignment marks have a square-grid pattern, the square-grid pattern having a pitch between about 0.2 μm and about 1 μm.

6. The method of claim 4 , wherein the plurality of alignment marks are formed in scribe lines separating individual dies on the substrate.

7. The method of claim 1 , wherein the recessing the second plurality of doped regions comprises:
recessing the second plurality of doped regions to each have a first depth, the first depth measured from a top surface of the corresponding second plurality of recessed doped regions to a top surface of the substrate.

8. The method of claim 7 , wherein the first depth is between about 100 Å and about 2000 Å.

9. The method of claim 1 , wherein the second plurality of recessed doped regions each have width between about 0.5 μm and about 20 μm.

10. A method comprising:
implanting a first region of a substrate with a first dopant to form a first plurality of doped regions;
implanting a second region of the substrate with the first dopant to form a second plurality of doped regions; and
recessing the second plurality of doped regions to have top surfaces below a top surface of the substrate to form a plurality of alignment marks.

11. The method of claim 10 , wherein the first region is a pixel region of an image sensor, and the second region is a frame cell region of the image sensor.

12. The method of claim 11 , wherein the image sensor is a non-shallow trench isolation (non-STI) image sensor.

13. The method of claim 10 , wherein the plurality of alignment marks comprises one or more zero layer alignment marks.

14. The method of claim 10 , wherein the plurality of alignment marks comprises one or more active area layer alignment marks.

15. The method of claim 14 , wherein the plurality of alignment marks have a square-grid pattern.

16. The method of claim 14 , wherein the plurality of alignment marks are formed in scribe lines separating individual dies on the substrate.

17. The method of claim 10 , wherein the first dopant comprises boron.

18. A method comprising:
forming a first mask over a first region and a second region of a substrate;
patterning the first mask to expose portions of the substrate in the first region and the second region;
implanting the exposed portions of the substrate in the first region and the second region to form a first plurality of doped regions and a second plurality of doped regions, respectively;
forming a second mask over the patterned first mask and the first plurality of doped regions in the first region of the substrate, the second plurality of doped regions being exposed through the second mask;
while the second mask is on the first region of the substrate, recessing the second plurality of doped regions to form a plurality of alignment marks; and
removing the second mask and the first mask.

19. The method of claim 18 , wherein the first region is a pixel region of an image sensor, and the second region is a frame cell region of the image sensor.

20. The method of claim 18 , wherein the first mask is a negative tone photoresist layer, and the second mask is a positive tone photoresist layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Cheng-Hsien
• Chen Sheng-Chau
• Chang Chun-Wei
• Hsu Kai-Chun
• Lai Chih-Yu
• Hsu Wei-Cheng
• Tseng Hsiao-Hui
• Chou Shih Pei
• Ting Shyh-Fann
• Hsu Tzu-Hsuan
• Wang Ching-Chun
• Tu Yeur-Luen
• Yaung Dun-Nian

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/501

  for use before dicing · CPC title