Semiconductor chip with thermal interface tape

Patent metadata

Field	Value
Publication number	US-9627281-B2
Application number	US-86025610-A
Country	US
Kind code	B2
Filing date	Aug 20, 2010
Priority date	Aug 20, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

First claim

What is claimed is:

1. A method of manufacturing, comprising:
applying a thermal interface tape to a side of a semiconductor wafer including at least one semiconductor chip, the at least one semiconductor chip having plural front side interconnects and plural backside interconnects, the thermal interface tape being positioned on the at least one semiconductor chip over the backside interconnects; and
singulating the at least one semiconductor chip from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

2. The method of claim 1 , comprising applying a wafer carrier tape to the thermal interface tape.

3. The method of claim 2 , comprising applying the wafer carrier tape to the thermal interface tape after the thermal interface tape is applied to the at least one semiconductor chip.

4. The method of claim 2 , comprising applying the wafer carrier tape to the thermal interface tape before the thermal interface tape is applied to the at least one semiconductor chip.

5. The method of claim 1 , wherein the thermal interface tape comprises a base and a thermal interface material coupled to the base, the thermal interface material contacting the side of the semiconductor wafer.

6. The method of claim 1 , comprising placing a heat spreader in thermal contact with the thermal interface tape and performing an electrical test on the at least one semiconductor chip.

7. The method of claim 6 , comprising removing the thermal interface tape after the electrical test and stacking another semiconductor chip on the at least one semiconductor chip.

8. A method of testing a semiconductor chip device, comprising:
applying a first thermal interface tape to a side of a first semiconductor chip of the semiconductor chip device, the first semiconductor chip having plural front side interconnects and plural backside interconnects, the first thermal interface tape being positioned over the backside interconnects;
placing a heat spreader in thermal contact with the first thermal interface tape; and
performing an electrical test on the first semiconductor chip.

9. The method of claim 8 , wherein the first thermal interface tape comprises a base and a thermal interface material coupled to the base, the thermal interface material contacting the side of the first semiconductor chip.

10. The method of claim 8 , comprising removing the first thermal interface tape after the electrical test and stacking a second semiconductor chip on the first semiconductor chip.

11. The method of claim 10 , comprising applying a second thermal interface tape to a side of the second semiconductor chip.

12. The method of claim 11 , comprising performing an electrical test on the first or the second semiconductor chips.

13. A method of manufacturing, comprising:
applying a thermal interface tape to a side of a semiconductor wafer including at least one semiconductor chip, the at least one semiconductor chip having plural front side interconnects and plural backside interconnects, the thermal interface material tape being positioned on the at least one semiconductor chip over the backside interconnects;
singulating the at least one semiconductor chip from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip; and
mounting the at least one semiconductor chip to a carrier substrate.

14. The method of claim 13 , comprising performing an electrical test on the at least one semiconductor chip.

15. The method of claim 14 , mounting an additional semiconductor chip on the at least one semiconductor chip.

16. The method of claim 15 , comprising placing a heat spreader in thermal contact with the thermal interface tape prior to the electrical test.

Assignees

• Prejean Seth
• Kent Dales
• Brandon Ronnie
• Refai-Ahmed Gamal
• Su Michael Z
• Bienek Michael
• Siegel Joseph
• Black Bryan
• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Prejean Seth
• Kent Dales
• Brandon Ronnie
• Refai-Ahmed Gamal
• Su Michael Z
• Bienek Michael
• Siegel Joseph
• Black Bryan

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P72/7442

  Separation by peeling · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title