Forming array contacts in semiconductor memories

Patent metadata

Field	Value
Publication number	US-9627251-B2
Application number	US-201514722889-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	Mar 16, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

First claim

What is claimed:

1. A method comprising:
forming a plurality of masks extending perpendicularly to a length of a plurality of filled trenches;
removing exposed portions of the plurality of filled trenches to form openings in the plurality of filled trenches; and
filling the openings to form contacts.

2. The method of claim 1 , wherein filling the openings comprises filling the openings with a metal.

3. The method of claim 1 , wherein the exposed portions of the plurality of filled trenches are removed by etching.

4. The method of claim 1 , further comprising removing the plurality of masks.

5. The method of claim 1 , further comprising:
removing an upper portion of the metal; and
removing an upper portion of the plurality of filled trenches.

6. The method of claim 5 , further comprising coupling the contacts to a metal line.

7. The method of claim 6 , further comprising forming the metal line and the contacts in the same metallization.

8. The method of claim 6 , further comprising forming the contacts and metal lines in a dual damascene process.

9. The method of claim 1 , further comprising forming parallel spaced active areas and forming the plurality of filled trenches parallel to the active areas.

10. The method of claim 9 , wherein the parallel spaced active areas are formed below the plurality of filled trenches.

11. The method of claim 1 , further comprising forming parallel spaced active areas and forming the plurality of filled trenches perpendicular to the active areas.

12. A method comprising:
forming a plurality of spaced openings along a length of a trench of a plurality of parallel spaced filled trenches over a memory array; and
forming array contacts in the plurality of spaced openings.

13. The method of claim 12 , wherein the plurality of parallel spaced filled trenches are formed in a dielectric over the memory array.

14. The method of claim 12 , wherein forming array contacts comprises filling the plurality of spaced openings with a metal.

15. The method of claim 12 , further comprising forming a plurality of parallel spaced masks extending transversely to the plurality of parallel spaced filled trenches prior to forming the plurality of spaced openings along the length of the trench of the plurality of parallel spaced filled trenches.

16. The method of claim 12 , further comprising removing an upper portion of the plurality of parallel spaced filled trenches.

17. The method of claim 16 , further comprising forming metal lines in the upper portion of the plurality of parallel spaced filled trenches.

18. The method of claim 12 , wherein forming the array contacts comprises forming the array contacts of metal lines in a dual damascene process.

19. The method of claim 12 , further comprising:
forming parallel spaced active areas; and
forming the plurality of parallel spaced filled trenches perpendicular to the parallel spaced active areas.

20. The method of claim 19 , wherein the parallel spaced active areas are formed below the plurality of parallel spaced filled trenches.

Assignees

• Micron Technology Inc

Inventors

• Somaschini Roberto
• Vaccaro Alessandro
• Tessariol Paolo
• Albini Giulio

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title