Forming array contacts in semiconductor memories

Patent metadata

Field	Value
Publication number	US-9059261-B2
Application number	US-201414302160-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Mar 16, 2010
Publication date	Jun 16, 2015
Grant date	Jun 16, 2015

Abstract

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

First claim

What is claimed:

1. A method, comprising:
filling parallel, spaced trenches formed through a dielectric layer with a filler material;
forming a plurality of masks extending perpendicularly to the length of said filled trenches;
etching the exposed portions of the filled trenches to form openings in the filled trenches; and
filling the openings with a metal.

2. The method of claim 1 , further comprising removing the plurality of masks.

3. The method of claim 1 , further comprising:
etching an upper portion of the metal; and
etching an upper portion of the filled trenches.

4. The method of claim 3 , further comprising forming array contacts coupled to a metal line.

5. The method of claim 4 , wherein the array contacts include the openings with the metal.

6. The method of claim 4 , further comprising forming the metal line and the array contacts in the same metallization.

7. The method of claim 1 , further comprising forming array contacts and metal lines in a dual damascene process.

8. The method of claim 1 , further comprising forming parallel spaced active areas and forming the trenches parallel to the active areas.

9. The method of claim 8 , wherein the parallel spaced active areas are formed below the trenches.

10. The method of claim 1 , further comprising forming parallel spaced active areas and forming said trenches perpendicular to the active areas.

11. A method comprising:
forming a plurality of parallel spaced filled trenches in a dielectric material formed over a memory array;
forming a plurality of spaced openings along the length of each of the trenches of the plurality of parallel spaced filled trenches; and
filling the plurality of spaced openings with a metal to form array contacts.

12. The method of claim 11 , further comprising forming a plurality of parallel spaced masks extending transversely to the plurality of parallel spaced filled trenches prior to forming a plurality of spaced openings along the length of each of the trenches of the plurality of parallel spaced filled trenches.

13. The method of claim 11 , further comprising etching an upper portion of the plurality of parallel spaced filled trenches.

14. The method of claim 13 , further comprising forming metal lines in the upper portion of the plurality of parallel spaced filled trenches.

15. The method of claim 11 , further comprising forming array contacts of metal lines in a dual damascene process.

16. The method of claim 11 , further comprising:
forming parallel spaced active areas; and
forming the plurality of parallel spaced filled trenches perpendicular to the parallel spaced active areas.

17. The method of claim 16 , wherein the parallel spaced active areas are formed below the plurality of parallel spaced filled trenches.

18. An apparatus, comprising:
a memory array;
a dielectric material over said memory array;
a filled trench in said dielectric material;
an opening along the length of the filled trench; and
an array contact formed in the opening.

19. The device of claim 18 , wherein the dielectric material comprises a pre-metal deposition oxide.

20. The device of claim 18 , further comprising an etch stop layer over the memory array below the dielectric material.

21. The device of claim 20 , wherein the etch stop layer comprises a borderless nitride.

Assignees

• Micron Technology Inc

Inventors

• Somaschini Roberto
• Vaccaro Alessandro
• Tessariol Paolo
• Albini Giulio

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title