High performance interconnect

Patent metadata

Field	Value
Publication number	US-9626321-B2
Application number	US-201314060191-A
Country	US
Kind code	B2
Filing date	Oct 22, 2013
Priority date	Oct 22, 2012
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

First claim

What is claimed is:

1. An apparatus comprising
a physical layer (PHY) configured to be coupled to a serial differential link that is to include a number of lanes, the PHY to include a transmitter and a receiver to be coupled to each lane of the number of lanes, wherein the transmitter to be coupled to each lane is configured to embed a clock with link layer data to be transmitted over at least a particular one of the lanes, and wherein the PHY is to periodically issue a blocking link state (BLS) request to cause a control window of a defined length to interrupt transmission of a stream of link layer flits on the particular lane, transition to transmission of one or more physical layer-associated control messages on the particular lane during the control window, and resume transmission of the link layer flits on the particular lane following the control window, wherein the physical layer-associated control messages cause one of an in-band reset, an entry into low power state, and an entry into a partial width state.

Assignees

• Intel Corp

Inventors

• Safranek Robert J
• Blankenship Robert G
• Iyer Venkatraman
• Willey Jeff
• Beers Robert
• Jue Darren S
• Kumar Arvind A
• Das Sharma Debendra
• Swanson Jeffrey C
• Fahim Bahaa
• Geetha Vedaraman
• Spink Aaron T
• Spagna Fulvio
• Shah Rahul R
• Iyer Sitaraman V
• Nale William Harry
• Das Abhishek
• Johnson Simon P
• Dhillon Yuvraj S
• Liu Yen-Cheng
• Ramanujan Raj K
• Maddox Robert A
• Hum Herbert H
• Gupta Ashish

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• H04L45/74

  Address processing for routing · CPC title

• G06F12/0806 Primary

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title