Mobile device and a method of controlling the mobile device

Patent metadata

Field	Value
Publication number	US-9626307-B2
Application number	US-201414303860-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jul 19, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A mobile device including: a storage device; a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; and a working memory including an input/output (I/O) scheduler and a device driver, the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.

First claim

What is claimed is:

1. A mobile device, comprising:
a storage device;
a system-on-chip (SOC) including a central processing unit (CPU), a performance controller and a memory interface configured to access the storage device in response to a request of the CPU; and
a working memory including an input/output (I/O) scheduler and a device driver,
the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue,
the device driver configured to adjust an access speed of the storage device based on the number of requests in the sync queue,
wherein the performance controller is configured to adjust a performance control mode of the SOC based on the number of requests in the sync queue,
wherein the performance control mode includes a dynamic voltage frequency scaling (DVFS) mode in which a driving voltage of the SOC and a frequency of a driving clock of the CPU are adjusted,
wherein the DVFS mode includes a plurality of levels, each level including a voltage and a frequency corresponding to a particular range of the number of requests in the synch queue, wherein a desired level is not activated until a prior activated level times out.

2. The mobile device of claim 1 , wherein when the sync queue and the async queue are empty a low power mode of the mobile device is entered.

3. The mobile device of claim 1 , wherein the CPU is a heterogeneous multi-core CPU.

4. The mobile device of claim 1 , wherein the working memory includes a dynamic random access memory (DRAM).

5. The mobile device of claim 1 , wherein the storage device includes a nonvolatile memory device.

6. The mobile device of claim 1 , wherein the synch queue includes a plurality of read requests.

7. The mobile device of claim 1 , wherein the async queue includes a plurality of write requests.

8. The mobile device of claim 1 , wherein the device driver is configured to change the frequency of the driving clock of the CPU and a frequency of a data transfer clock of the memory interface.

9. The mobile device of claim 1 , wherein the device driver is configured to change the driving voltage of the SOC and the frequency of the driving dock of the CPU.

10. The mobile device of claim 1 , wherein the device driver is configured to change a number of cores operating in the CPU.

11. A mobile device, comprising:
a storage device;
a central processing unit (CPU);
a memory interface configured to interface with a high speed data transfer device;
a working memory including a module, the module including an input/output (I/O) scheduler, a performance control module and a device driver,
the I/O scheduler including an aspic request queue configured to store non-real time processing requests by user input and a sync request queue configured to store real time processing requests by the user input,
the device driver configured to adjust an access speed of the storage device based on the number of requests in the sync request queue,
the performance, controller configured to adjust a performance control mode of the CPU based on the number of requests in the sync request queue,
wherein the performance control mode includes a quality of service (QOS) mode in which a frequency of a driving clock of the CPU and a frequency of a data transfer clock of the memory interface are adjusted,
wherein the QOS mode includes a plurality of steps, each step including a CPU frequency and a memory interface frequency corresponding to a particular range of the number of requests in the synch queue, wherein a desired step is not activated until a prior activated step times out.

12. The mobile device of claim 11 , wherein the high speed data transfer device is the storage device.

13. The mobile device of claim 11 , wherein the performance control mode of the mobile device includes a dynamic voltage frequency scaling (DVFS) mode in which a driving voltage of the mobile device and the frequency of the driving clock of the CPU are adjusted.

14. The mobile device of claim 13 , wherein the DVFS mode includes a plurality of levels, each level including a voltage and a frequency corresponding to a particular range of the number of requests in the synch queue, wherein a desired level is not activated until a prior activated level times out.

15. The mobile device of claim 11 , wherein the performance control mode of the mobile device includes a CPU mode in which a number of cores operating in the CPU is adjusted.

16. The mobile device of claim 15 , wherein the CPU mode includes a plurality of modes, each mode including a core of the CPU to be activated for a particular range of the number of requests in the synch queue, wherein a desired mode is not activated until a prior activated mode times out.

17. The mobile device of claim 11 , wherein the display screen is a touch screen.

18. The mobile device of claim 11 , wherein the module is a kernel.

19. A method of controlling a mobile device, comprising:
storing real time processing requests in a sync queue and non real time processing requests in an async queue of an input/output (I/O) scheduler of a working memory;
determining, with a device driver of the working memory, a performance control mode of the mobile device based on the number of requests stored in the sync queue;
increasing a data transfer rate between a memory interface and a storage device when the number of requests in the sync queue is greater than a predetermined threshold; and
decreasing the data transfer rate between the memory interface and the storage device when the number of requests in the sync queue is less than the predetermined threshold,
wherein the data transfer rate is not increased or decreased until a time limit associated with a previous data transfer rate elapses,
wherein the performance control mode includes a central processing unit (CPU) mode, a dynamic voltage frequency scaling (DVFS) mode or a quality of service (QOS) mode,
wherein the CPU mode includes a plurality of modes, each mode including a core of the CPU to be activated for a particular range of the number of requests in the synch queue,
wherein the DVFS mode includes a plurality of levels, each level including a voltage and a frequency corresponding to a particular range of the number of requests in the synch queue,
wherein the QOS mode includes a plurality of steps, each step including a CPU frequency and a memory interface frequency corresponding to a particular range of the number of quests in the synch queue.

20. The method of claim 19 , further comprising entering a low power mode of the mobile device when the sync queue and the async queue are empty.

21. The method of claim 19 , wherein the sync queue includes a plurality of read requests and the async queue includes a plurality of write requests.

22. The method of claim 19 , wherein the CPU mode is entered prior to the QOS mode and the DVFS mode.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Kim Ho-Sung

Classifications

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F2213/3804

  Memory card connected to a computer port directly or by means of a reader/writer · CPC title

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F13/20

  for access to input/output bus · CPC title