Processor performance monitoring unit synchronization

Patent metadata

Field	Value
Publication number	US-9626229-B1
Application number	US-201614990102-A
Country	US
Kind code	B1
Filing date	Jan 7, 2016
Priority date	Jan 7, 2016
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method for monitoring performance of events occurring in a multiprocessor system is provided where the performance monitoring units (PMUs) are globally synchronized. The global synchronization is carried out with a dedicated bit field set to any of pause, stop, restart, or reset command. The command is sent across the scan communications interface (SCOM) of all chips by using existing fabric connecting all nest units to control the PMUs in the system. A pre-scale counter before a main counter may be used to buffer event counts until a reset or a restart command is sent to the SCOM in the system.

First claim

The invention claimed is:

1. A computer implemented method to monitoring performance of events occurring in a multiprocessor system, the method comprising:
providing a register operation that includes a bit field command set to at least one of a pause, a stop, a restart, or reset operation; and
sending the bit field command across a scan communications interface (SCOM) using a computing fabric,
wherein sending the bit field command across the SCOM globally synchronizes a plurality of performance monitoring units (PMUs).

2. The method of claim 1 , wherein the plurality of PMUs are set to freeze upon receiving the bit field command.

3. The method of claim 1 , wherein the plurality of PMUs are set to freeze periodically upon receiving the bit field command.

4. The method of claim 1 , wherein sending the bit field command across the SCOM further comprises sending a Powerbus type pmisc to the plurality of PMUs.

5. The method of claim 4 , wherein the global synchronization of the PMUs provides correlation of counter values from nest units in the system.

6. The method of claim 5 , wherein the correlation of values from nest units in the system occurs during any period of the pause and the reset operations.

7. The method of claim 5 , wherein the correlation of values from nest units in the system occurs during any period of a stop and a restart operation.

8. The method of claim 1 , further comprising providing a pre-scale counter before a main counter.

9. The method of claim 8 , wherein the pre-scale counter buffers event counts until a bit field command of the reset or restart operation is sent to the SCOM in the system.

10. The method of claim 1 , further comprising setting the bit field command is set to the pause operation.

11. The method of claim 10 , further comprising:
copying active counters to back-up counters;
resting active counters to zero; and
resuming counting.

12. The method of claim 11 , further comprising reading the back-up counters.

13. A multi-processor system comprising:
a plurality of processor units, wherein each processor unit generates signals representing occurrences of events at the processor unit, wherein each processor unit includes a scan communication interface (SCOM);
a plurality of performance monitoring units (PMUs) for monitoring performance of the events at the processor units;
a register operation with a bit field command set to any of pause, stop, restart, or reset; and
a non-transitory computer-readable storage medium comprising instructions executable to send the bit field command across the SCOM by using a computing fabric to globally synchronize the PMUs in the system, wherein the plurality of processor units and the plurality of performance monitoring units are implement by the multi-processor system.

14. The system of claim 13 , wherein sending the bit field command across the SCOM includes sending a powerbus type pmisc to the PMUs in the system.

15. The system of claim 13 , wherein the global synchronization of the PMUs in the system provides correlation of counter values from nest units in the system.

16. The system of claim 13 , further comprising a plurality of performance counters to count signals representing occurrences of events at the plurality of the processor units.

17. A non-transitory computer-readable storage medium comprising operational instructions that, when executed by a processor, cause the processor to:
provide a register operation that includes a bit field command set to at least one of a pause, a stop, a restart, or reset operation; and
send the bit field command across a scan communications interface (SCOM) by using a computing fabric,
wherein sending the bit field command across the SCOM globally synchronizes a plurality of performance monitoring units (PMUs).

18. The computer-readable storage medium of claim 17 , wherein the global synchronization of the PMUs provides correlation of counter values from nest units in the system.

19. The computer-readable storage medium of claim 18 , wherein the correlation of values from nest units in the system occurs during any period of the pause and the reset operations.

20. The computer-readable storage medium of claim 17 , wherein a pre-scale counter is provided before a main counter.

Assignees

• IBM

Inventors

• Krolak David J
• Marino Charles F
• Nair Sooraj R
• Purushotham Srinivas
• Ramani Srinivasan

Classifications

• G06F11/3495 Primary

  for systems · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F11/3006

  where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title