Method of forming a circuit board

Patent metadata

Field	Value
Publication number	US-9622350-B2
Application number	US-201314040637-A
Country	US
Kind code	B2
Filing date	Sep 28, 2013
Priority date	Sep 28, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

First claim

What is claimed is:

1. A method of forming a circuit board upon which to mount an integrated circuit chip, the method comprising:
forming a first interconnect zone on a surface of the circuit board, the first interconnect zone having a first area on the surface of the circuit board, the first interconnect zone including a first plurality of contacts having a first pitch at the surface of the circuit board; and
forming a second interconnect zone on the surface of the circuit board, the second interconnect zone having a second area on the surface of the circuit board, the second area having an inner perimeter surrounding all sides of an outer perimeter of the first area on the surface, the second interconnect zone including a second plurality of contacts or traces having a second pitch at the surface of the circuit board, wherein the first pitch is a distance from a center of one contact of the first plurality of contacts to a center of an adjacent contact of the first plurality of contacts; and the second pitch is a distance from a center of a first contact or trace of one of the second plurality of contacts or traces to a center of an adjacent contact or trace of the second plurality of contacts or traces, and wherein the first pitch is smaller than the second pitch.

2. The method of claim 1 , wherein the circuit board comprises a plurality of interconnect layers, each interconnect layer including a layer of dielectric material, a plurality of interconnects at a first surface of the layer of dielectric material and a plurality of contacts at a second surface of the layer of dielectric material, wherein the interconnects are attached to the contacts.

3. The method of claim 1 , wherein forming the first plurality of contacts comprises:
transferring a transfer substrate having the first contacts onto the surface of the circuit board, wherein transferring includes transferring the first contacts: (1) into a dielectric material of the circuit board below the surface of the circuit board prior to curing the dielectric material of the circuit board, and (2) within the first interconnect zone.

4. The method of claim 3 , wherein transferring includes, after transferring and curing, removing the transfer substrate from the surface of the circuit board and leaving the first contacts below the surface of the circuit board.

5. The method of claim 3 , wherein the transfer substrate is formed by:
lithographically patterning a surface of a dielectric layer with the breakout pattern; then
plating the breakout pattern with conductor; then
DFR stripping the conductor; and then
singulating the dielectric to produce a number of transfer substrates.

6. The method of claim 1 , wherein forming the first plurality of contacts comprises:
laser scribing a pattern of trenches, at locations for the first contacts, into a surface of the circuit board and within the first interconnect zone; and then
forming conductive material in the patterned trenches to form the first contacts.

7. The method of claim 6 , wherein laser scribing comprises laser projection and patterning (LPP) ablated traces of a pattern of trenches of the first contacts into a surface of the first interconnect zone; and wherein forming conductive material comprises filling the trenches with copper using electro-less or electrolytic plating of copper.

8. The method of claim 1 , wherein the second area completely surrounds the first area on the surface of the circuit board.

9. The method of claim 1 , wherein forming the first plurality of contacts comprises forming the first contacts using electronic device fabrication processing according to a design rule appropriate for direct chip attachment (DCA) of integrated circuit chip contacts to contacts of a substrate package to be mounted onto a circuit board; and wherein forming the second plurality of contacts or traces comprises forming traces to the first contacts using electronic device fabrication processing according to a design rule appropriate for direct attachment of substrate package contacts to contacts of a motherboard.

10. The method of claim 1 , wherein the first pitch comprises a first pitch distance between midpoints of the first plurality of contacts of between 120 microns and 160 microns; and wherein the second pitch comprises a second pitch distance between midpoints of the second plurality of contacts or traces of between 390 microns and 410 microns.

11. The method of claim 1 , wherein the first zone comprises a first square outer perimeter having first side lengths of between 9 mm and 11 mm; and wherein the second zone comprises a second square outer perimeter having second side lengths of between 14 mm and 18 mm.

12. The method of claim 1 , further comprising:
direct chip attaching contacts of the integrated circuit chip to the first plurality of contacts; and
mounting the circuit board in one of a tablet computer, a smartphone, and a value phone.

Assignees

• Roy Mihir K
• Manusharow Mathew J
• Intel Corp

Inventors

• Roy Mihir K
• Manusharow Mathew J

Classifications

• H05K1/141 Primary

  One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence) · CPC title

• H05K3/207 Primary

  using a prefabricated paste pattern, ink pattern or powder pattern · CPC title

• H05K3/107

  by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence) · CPC title

• Y10T29/49128

  Assembling formed circuit to base · CPC title

• H05K2201/10734

  Ball grid array [BGA]; Bump grid array · CPC title