Power semiconductor device

Patent metadata

Field	Value
Publication number	US-9620631-B2
Application number	US-201313846624-A
Country	US
Kind code	B2
Filing date	Mar 18, 2013
Priority date	Sep 12, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.

First claim

What is claimed is:

1. A power semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a pair of conductive bodies provided in the second semiconductor layer via an insulating film;
a third semiconductor layer of the second conductivity type selectively provided on the second semiconductor layer;
a first electrode provided on the pair of conductive bodies, the first electrode being electrically connected to the pair of conductive bodies; and
a second electrode electrically connected to the first semiconductor layer,
wherein the second semiconductor layer includes a region of the second conductivity type provided under one of the pair of conductive bodies, the region of the second conductivity type being connected to the second semiconductor layer between the pair of conductive bodies,
wherein a total second conductivity type impurity amount per unit area of the second semiconductor layer is 2×10 12 /cm 2 or less,
wherein a distance between the pair of conductive bodies via the insulating film is 2 μm or less,
wherein the first semiconductor layer includes a first region and a second region adjacent to the first region, and the second semiconductor layer, the pair of conductive bodies, and the third semiconductor layer are provided on the first semiconductor layer in the first region,
wherein the device further includes:
a fifth semiconductor layer of the second conductivity type, the fifth semiconductor layer being provided on the first semiconductor layer in the second region, and the fifth semiconductor layer having a higher second conductivity type impurity concentration than the second semiconductor layer;
a sixth semiconductor layer of the first conductivity type, the sixth semiconductor layer being selectively provided on the fifth semiconductor layer, and the sixth semiconductor layer having a higher first conductivity type impurity concentration than the first semiconductor layer; and
a gate electrode provided on the first semiconductor layer in the second region, the fifth semiconductor layer, and the sixth semiconductor layer via a gate insulating film, and

wherein the first electrode is electrically connected to the fifth semiconductor layer and the sixth semiconductor layer.

2. The device according to claim 1 , wherein the second semiconductor layer is in schottky contact with the first electrode.

3. The device according to claim 1 , wherein a ratio of A to B is smaller than or equal to 0.5,where A is the distance between the pair of conductive bodies via the insulating film and B is a depth of the insulating film and one of the pair of conductive bodies.

4. The device according to claim 1 , wherein the gate electrode extends from a surface of the sixth semiconductor layer through the fifth semiconductor layer to the first semiconductor layer via the gate insulating film.

5. The device according to claim 4 , wherein a depth of one of the conductive bodies and the insulating film is the same as a depth of the gate electrode and the gate insulating film.

6. The device according to claim 1 , further comprising an eighth semiconductor layer of the second conductivity type, the eighth semiconductor layer being electrically connected to the first semiconductor layer in the second region, and the eighth semiconductor layer having a higher second conductivity type impurity concentration than the fifth semiconductor layer,
wherein the second electrode is electrically connected to the first semiconductor layer via the eighth semiconductor layer in the second region.

7. The device according to claim 1 , wherein the third semiconductor layer is provided between the pair of conductive bodies.

8. The device according to claim 1 , wherein a portion of the second semiconductor layer is provided between the third semiconductor layer and each of the pair of conductive bodies.

9. A power semiconductor device comprising:
a first semiconductor layer of a first conductivity type, the first semiconductor layer including a first region and a second region adjacent to the first region;
a second semiconductor layer of a second conductivity type, the second semiconductor layer being provided on the first semiconductor layer in the first region;
a pair of conductive bodies provided in the first semiconductor layer and the second semiconductor layer via an insulating film, the pair of conductive bodies being adjacent to the second semiconductor layer via the insulating film;
an impurity diffusion layer of the second conductivity type, the impurity diffusion layer being provided under the pair of conductive bodies;
a fifth semiconductor layer of the second conductivity type, the fifth semiconductor layer being provided on the first semiconductor layer in the second region, and the fifth semiconductor layer having a higher second conductivity type impurity concentration than the second semiconductor layer;
a sixth semiconductor layer of the first conductivity type, the sixth semiconductor layer being selectively provided on the fifth semiconductor layer, and the sixth semiconductor layer having a higher first conductivity type impurity concentration than the first semiconductor layer;
a gate electrode provided on the first semiconductor layer in the second region, the fifth semiconductor layer, and the sixth semiconductor layer via a gate insulating film;
a first electrode provided on the pair of conductive bodies, the fifth semiconductor layer, and the sixth semiconductor layer, the first electrode being electrically connected to the pair of conductive bodies, the fifth semiconductor layer, and the sixth semiconductor layer; and
a second electrode electrically connected to the first semiconductor layer.

10. The device according to claim 9 , wherein the impurity diffusion layer is formed by ion-implanting a second conductivity type impurity into a portion of the first semiconductor layer adjacent to a bottom of the pair of conductive bodies via the insulating film.

11. The device according to claim 9 , wherein the impurity diffusion layer protrudes further to the first semiconductor layer side than a bottom of the second semiconductor layer.

12. The device according to claim 9 , wherein the impurity diffusion layer is connected to the second semiconductor layer along a side wall of the pair of conductive bodies via the insulating film.

13. The device according to claim 9 , wherein the impurity diffusion layer is away from the second semiconductor layer via the first semiconductor layer.

14. The device according to claim 9 , further comprising a third semiconductor layer of the second conductivity type, the third semiconductor layer being selectively provided on the second semiconductor layer between the pair of conductive bodies,
wherein a second conductivity type impurity concentration in a surface of the third semiconductor layer is higher than a second conductivity type impurity concentration in a surface of the second semiconductor layer,
wherein a total second conductivity type impurity amount per unit area of the third semiconductor layer is larger than a total second conductivity type impurity amount per unit area of the second semiconductor layer, and
wherein the first electrode is electrically connected to the third semiconductor layer.

15. The device according to claim 14 , further comprising a seventh semiconductor layer of the first conductivity type, the seventh semiconductor layer being selectively provided on the second semiconductor layer between the pair

Assignees

• Toshiba Kk

Inventors

• Matsudai Tomoko
• Ogura Tsuneo
• Oshino Yuichi
• Ninomiya Hideaki
• Nakamura Kazutoshi

Classifications

• H01L29/36

  Electricity · mapped topic

• H01L29/7397 Primary

  Electricity · mapped topic

• H01L29/868

  Electricity · mapped topic

• H01L29/0626

  Electricity · mapped topic

• H01L29/0688

  Electricity · mapped topic