Semiconductor structure containing low-resistance source and drain contacts

Patent metadata

Field	Value
Publication number	US-2016336323-A1
Application number	US-201615220123-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	Nov 21, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, said method comprising:
providing a structure comprising at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion, and wherein a surface of said first epitaxial semiconductor material includes a high k dielectric layer disposed thereon; forming a layer of a dipole metal or a metal-insulator-semiconductor oxide on said second epitaxial semiconductor material, but not said first epitaxial semiconductor material; removing said high k dielectric layer from said surface of said first epitaxial semiconductor material; and forming a first metal semiconductor alloy on said first epitaxial semiconductor material and a second metal semiconductor alloy in direct contact with said layer of said dipole metal or said metal-insulator-semiconductor oxide.

2 . The method of claim 1 , further comprising forming an additional semiconductor material atop at least one of the first epitaxial semiconductor material and said second epitaxial semiconductor material and patterning said additional semiconductor material prior to forming said first and second metal semiconductor alloys.

3 . The method of claim 1 , wherein said layer of dipole metal comprises a metal selected from the group consisting of Y, Er, Al, W, Ti, Hf, Zr, Zn, Be, La, Dy, Ye, Gd, Er, Yb and multilayers thereof.

4 . The method of claim 1 , wherein said layer of said metal-insulator-semiconductor oxide is selected from one of SiO x N y , GeO x , AlO x , Ge 3 N 4 , TiO 2 , HfO 2 , ZrO 2 , ZnO.Be x O y , La x O y , Dy x O y , Ye x O y , Gd x O y , Er x O y , and Yb x O y , wherein x and y are a content of a fraction.

5 . The method of claim 1 , wherein a trench isolation structure separates said first semiconductor material portion from said second semiconductor material portion.

6 . The method of claim 1 , wherein said first semiconductor material portion comprises a first semiconductor fin, and said second semiconductor material portion comprises a second semiconductor fin.

7 . A semiconductor structure comprising:
at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion; a layer of a dipole metal or a metal-insulator-semiconductor oxide present on said second epitaxial semiconductor material, but not said first epitaxial semiconductor material; a first metal semiconductor alloy in direct physical contact with said first epitaxial semiconductor material; and a second metal semiconductor alloy in direct contact with said layer of said dipole metal or said metal-insulator-semiconductor oxide.

8 . The semiconductor structure of claim 7 , wherein said layer of dipole metal comprises a metal selected from the group consisting of Y, Er, Al, W, Ti, Hf, Zr, Zn, Be, La, Dy, Ye, Gd, Er, Yb and multilayers thereof.

9 . The semiconductor structure of claim 7 , wherein said layer of said metal-insulator-semiconductor oxide is selected from one of SiO x N y , GeO x , AlO x , Ge 3 N 4 , TiO 2 , HfO 2 , ZrO 2 , ZnO.Be x O y , La x O y , Dy x O y , Ye x O y , Gd x O y , Er x O y , and Yb x O y , wherein x and y are a content of a fraction.

10 . The semiconductor structure of claim 7 , further comprising an additional semiconductor material atop at least one of the first epitaxial semiconductor material and said second epitaxial semiconductor material and patterning said additional semiconductor material prior to forming said first and second metal semiconductor alloys.

11 . The semiconductor structure of claim 10 , wherein said additional semiconductor material has a patterned topmost surface or a patterned sidewall surface.

12 . The semiconductor structure of claim 7 , wherein a trench isolation structure separates said first semiconductor material portion from said second semiconductor material portion.

13 . The semiconductor structure of claim 7 , wherein said first semiconductor material portion comprises a first semiconductor fin, and said second semiconductor material portion comprises a second semiconductor fin.

14 . A semiconductor structure comprising:
at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion; and an additional semiconductor material atop at least one of the first epitaxial semiconductor material and said second epitaxial semiconductor material, wherein said additional semiconductor material has a patterned topmost surface or a patterned sidewall surface.

15 . The method of claim 14 , wherein a trench isolation structure separates said first semiconductor material portion from said second semiconductor material portion.

16 . The method of claim 14 , wherein said first semiconductor material portion comprises a first semiconductor fin, and said second semiconductor material portion comprises a second semiconductor fin.

Assignees

• IBM

Inventors

• Ok Injo
• Pranatharthiharan Balasubramanian
• Surisetty Charan Veera Venkata Satya

Classifications

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111

  to Group IV semiconductors · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title