Integrated Schottky diode in high voltage semiconductor device

Patent metadata

Field	Value
Publication number	US-9620584-B2
Application number	US-201414454696-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Aug 31, 2009
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area comprising:
growing and patterning a field oxide layer in said termination area and also in said active cell are on a top surface of said semiconductor substrate wherein the field oxide layer in the termination area is patterned into a plurality of field oxide segments with a gap between two adjacent segments;
growing a gate oxide layer on said top surface of said semiconductor substrate followed by depositing and patterning a polysilicon layer to form a gate segment on top of the gate oxide layer in the active cell area at a gap distance away from said field oxide layer in the active cell area and patterning the polysilicon layer in the termination area for partially covering a top surface of the field segments, a sidewall of the field oxide segments and partially over a part of the gap between the field oxide segments in the termination area; and
performing a blank body dopant implant to form body dopant regions substantially aligned with said gap between the field oxide layer and the gate segment in the active cell area followed by diffusing said body dopant regions into body regions in the active cell area of said semiconductor substrate and wherein the blank body dopant implant also simultaneously forming guard rings in the semiconductor substrate not covered by the field oxide segments in the termination area.

2. The method of claim 1 further comprising:
implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than said body regions in the active cell area and in the guard rings in the termination area and
applying a source mask to block the guard rings in the termination area to implant source regions having a conductivity opposite to said body region in the active cell area with said source regions encompassed in said body regions and surrounded by said high concentration body-dopant regions.

3. The method of claim 2 further comprising:
depositing an insulation layer on top of said semiconductor power device and applying a contact metal mask to open contact openings to contact the body and source regions in the active cell area and the guard rings in the termination area followed by removing said field oxide in the active cell area; and
depositing a Schottky metal layer filling in said contact openings to contact said body regions and said source regions to form integrated Schottky diodes for said semiconductor power device in said active cell area.

4. The method of 2 further comprising:
depositing an insulation layer on top of said semiconductor power device and applying a contact metal mask to open contact openings to contact the body and source regions in the active cell area and the guard rings in the termination area followed by removing said field oxide in the active cell area; and
implanting a hallow body-dopant regions disposed adjacent to said body regions immediately below said top surface of said semiconductor substrate having a depth significantly shallower than said body regions.

5. The method of claim 2 wherein:
said step of performing a blank body dopant implant comprises a step of implanting a P-type dopant to said body dopant region in an N-type epitaxial layer supported on a N-type semiconductor substrate and implanting N type source regions encompassed in said P-type body-regions.

6. The method of claim 2 wherein:
said step of performing a blank body dopant implant comprises a step of implanting a N-type dopant to said body dopant region in an P-type epitaxial layer supported on a P-type semiconductor substrate and implanting P-type source regions encompassed in said N-type body-regions.

7. The method of claim 2 wherein:
said step of manufacturing said semiconductor power device further comprises a step of manufacturing a MOSFET power device.

8. The method of claim 2 wherein:
said step of manufacturing said semiconductor power device further comprises a step of manufacturing an IGBT power device.

9. The method of claim 3 wherein:
said step of manufacturing said semiconductor power device further comprises a step of manufacturing an IGBT power device in a an N-type semiconductor substrate and implanting a P-type bottom layer with N-type dopant regions near a bottom surface of said semiconductor substrate corresponding to said integrated Schottky diodes in said active cell area.

10. The method of claim 2 wherein:
said step of manufacturing said semiconductor power device further comprises a step of manufacturing a superjunction semiconductor substrate by forming in said semiconductor substrate alternating N-type and P-type dopant columns in said semiconductor substrate below said body-dopant regions before the step of growing and patterning the field oxide layer.

11. The method of claim 2 wherein:
said step of manufacturing said semiconductor power device further comprises a step of manufacturing a superjunction semiconductor substrate by forming said semiconductor substrate in a N-type semiconductor substrate with P-type columns underneath said body dopant regions doped with a P-type dopant and N-type columns between said P-type columns before the step of growing and patterning the field oxide layer.

Assignees

• Guan Lingpeng
• Bhalla Anup
• Bobde Madhur
• Zhu Tinggang
• Alpha & Omega Semiconductor

Inventors

• Guan Lingpeng
• Bhalla Anup
• Bobde Madhur
• Zhu Tinggang

Classifications

• H01L29/66712

  Electricity · mapped topic

• H01L29/0634 Primary

  Electricity · mapped topic

• H01L29/7395

  Electricity · mapped topic

• H01L29/66333

  Electricity · mapped topic

• H10D64/683

  being parallel to the channel plane · CPC title