Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9620515-B2
Application number	US-201514819706-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	May 13, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction in a first region. The semiconductor memory device also includes a first electrode film provided on a side of the semiconductor pillar and extending in a second direction different from the first direction in the first region and in a second region adjacent to the first region in the second direction. The semiconductor memory device also includes a second electrode film provided between the semiconductor pillar and the first electrode film in the first region. Film thickness in the first direction of the first electrode film in the first region is smaller than film thickness in the first direction of the first electrode film in the second region.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor pillar extending in a first direction in a first region;
a first electrode film provided on a second direction side of the semiconductor pillar and extending in a third direction in the first region and in a second region adjacent to the first region in the third direction, the second direction being different from the first direction, the third direction being different from the first direction and the second direction;
a second electrode film provided between the semiconductor pillar and the first electrode film in the first region;
a first insulating film provided between the semiconductor pillar and the second electrode film;
a second insulating film provided between the second electrode film and the first electrode film;
a third insulating film provided between the second insulating film and the first electrode film;
a fourth insulating film provided between the third insulating film and the first electrode film; and
a contact provided in the second region and connected to the first electrode film,
a film thickness in the first direction of the first electrode film in the first region being smaller than a film thickness in the first direction of the first electrode film in the second region.

2. A semiconductor memory device comprising:
a semiconductor pillar extending in a first direction in a first region;
a stacked body in which a first electrode film provided on a second direction side of the semiconductor pillar and extending in a third direction and an interlayer insulating film are alternately stacked in the first direction, the second direction being different from the first direction, the third direction being different from the first direction and the second direction;
a second electrode film provided between the semiconductor pillar and the first electrode film in the first region;
a first insulating film provided between the semiconductor pillar and the second electrode film;
a second insulating film provided between the second electrode film and the first electrode film;
a third insulating film provided between the second insulating film and the first electrode film;
a fourth insulating film provided between the third insulating film and the first electrode film; and
a contact provided in a second region adjacent to the first region and connected to the first electrode film,
the first electrode film and the interlayer insulating film being disposed not via the fourth insulating film in the second region.

3. The device according to claim 2 , wherein, in an adjacent region of a contact connecting section, which is a connecting portion of the first electrode film and the contact, the first electrode film and the interlayer insulating film are disposed between the first electrode film and the interlayer insulating film not via the fourth insulating film.

4. The device according to claim 2 , wherein the second region is a region including an end portion on the second direction side of the first electrode film.

5. The device according to claim 2 , wherein
the second region includes end portions on the second direction side of a plurality of the first electrode films mutually distal in the first direction, and
positions in the second direction of the end portions are different from each other.

6. The device according to claim 2 , wherein film thickness in the first direction of the first electrode film in the first region is smaller than film thickness in the first direction of the first electrode film in the second region.

7. The device according to claim 2 , wherein
in the first region, the third insulating film and the fourth insulating film are provided between the first electrode film and the interlayer insulating film, and
in the second region, the fourth insulating film is not provided between the first electrode film and the interlayer insulating film.

8. The device according to claim 2 , wherein, in the second region, the first electrode film and the interlayer insulating film are in direct contact with each other.

9. The device according to claim 2 , wherein
the third insulating film extends in the second region, and
the third insulating film is disposed between the first electrode film and the interlayer insulating film as well.

10. The device according to claim 2 , wherein the third insulating film includes a silicon oxide film.

11. The device according to claim 2 , wherein the second insulating film is a silicon nitride film, an oxide film containing aluminum, hafnium, or zirconium, a mixed film of the silicon nitride film and the oxide film, or a film obtained by adding metal to the mixed film.

12. The device according to claim 2 , wherein the fourth insulating film is a silicon nitride film, an oxide film containing aluminum, hafnium, or zirconium, or a mixed film of the silicon nitride film and the oxide film.

Assignees

• Toshiba Kk

Inventors

• Nagashima Satoshi
• Kato Tatsuya
• Kikutani Keisuke

Classifications

• H01L27/11556 Primary

  Electricity · mapped topic

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/40

  characterised by the peripheral circuit region · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title