Apparatus for SRAM cells

Patent metadata

Field	Value
Publication number	US-8976573-B2
Application number	US-201213446220-A
Country	US
Kind code	B2
Filing date	Apr 13, 2012
Priority date	Apr 13, 2012
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line.

First claim

What is claimed is:

1. An apparatus comprising:
a dielectric layer comprising a gate structure;
a first word line formed in a first metal layer, wherein the first word line extends in a first direction and the first metal layer is formed over the dielectric layer and in direct contact with the dielectric layer;
a first VSS line, a first bit line, a first power source line, a second bit line and a second VSS line formed in a second metal layer, wherein the first VSS line, the f…

Assignees

• Liaw Jhon-Jhy
• Taiwan Semiconductor Mfg

Inventors

• Liaw Jhon-Jhy

Classifications

• H10D30/62

  Electricity · mapped topic

• H10D89/10

  Electricity · mapped topic

• G11C11/412

  Physics · mapped topic

• G11C8/14 Primary

  Physics · mapped topic

• H10B10/12 Primary

  Electricity · mapped topic