Method for manufacturing silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-9620358-B2
Application number	US-201414892972-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	Jun 13, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.

First claim

The invention claimed is:

1. A method for manufacturing a silicon carbide semiconductor device, comprising steps of:
preparing a first silicon carbide layer having a first main surface and a second main surface opposite to said first main surface;
forming a first recess in said first main surface of said first silicon carbide layer, said first recess including a side portion continuously connected to said first main surface and a bottom portion continuously connected to said side portion;
forming a second silicon carbide layer in contact with said first main surface, said side portion, and said bottom portion, said second silicon carbide layer having a third main surface in contact with said first main surface and a fourth main surface opposite to said third main surface;
obtaining an image of a second recess formed in said fourth main surface at a position facing said first recess; and
performing alignment based on said image of said second recess,
said first main surface corresponding to a plane angled off relative to a {0001} plane such that a normal line vector of said first main surface has at least one of components of <11-20> and <1-100>,
a ratio obtained by dividing a depth of said first recess by a thickness of said second silicon carbide layer being more than 0.2.

2. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , wherein a size of an opening of said first recess in an in-plane off direction is less than a size of said opening of said first recess in a direction perpendicular to said in-plane off direction.

3. The method for manufacturing the silicon carbide semiconductor device according to claim 2 , wherein the size of the opening of said first recess in said in-plane off direction is not less than 2 μm and not more than 15 μm.

4. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , wherein said second recess is an alignment mark used in an exposure process.

5. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , wherein the thickness of said second silicon carbide layer is not less than 0.5 μm and not more than 5 μm.

6. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , wherein in the step of forming said first recess, said first recess is formed on a dicing line of said first main surface.

7. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , further comprising a step of forming a first impurity region in said first silicon carbide layer after the step of forming said first silicon carbide layer.

8. The method for manufacturing the silicon carbide semiconductor device according to claim 1 , further comprising a step of forming at least one of a second impurity region and an electrode after the step of performing the alignment based on said image of said second recess.

Assignees

• Sumitomo Electric Industries

Inventors

• Tamaso Hideto

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P14/3408 Primary

  Silicon carbide · CPC title