System and method for intelligent platform management interface keyboard controller style interface multiplexing

Patent metadata

Field	Value
Publication number	US-9619415-B2
Application number	US-201213691483-A
Country	US
Kind code	B2
Filing date	Nov 30, 2012
Priority date	Nov 30, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

First claim

What is claimed is:

1. An information handling system comprising:
a first processor core;
a first input/output (I/O) module coupled to the first processor core via a first direct media interface; and
a service processor coupled to the first I/O module via a multi-master interface;
wherein the first processor core sends a first low pin count (LPC) transaction for the service processor via the first direct media interface and the multi-master interface, such that the first LPC transaction is not transmitted via an LPC bus;
wherein the first LPC transaction is intercepted by a first I/O trap of the first I/O module;
wherein the first I/O module is operable to generate a first system management interrupt in response to the first LPC transaction being intercepted by the first I/O trap;
wherein the first system management interrupt is received by a first system management interrupt handler of the first processor core; and
the first system management interrupt handler redirects the first transaction to the first direct media interface.

2. The information handling system of claim 1 , further comprising:
a second processor core; and
a second input/output (I/O) module coupled to the first processor core via a second direct media interface;
wherein:
the service processor is coupled to the second I/O module via the multi-master interface; and
the second processor core sends a second LPC transaction for the service processor via the second direct media interface and the multi-master interface.

3. The information handling system of claim 2 , wherein:
the second LPC transaction is intercepted by a second I/O trap of the second I/O module, such that the second LPC transaction is not transmitted via the LPC bus;
the second I/O module is operable to generate a second system management interrupt in response to the second LPC transaction being intercepted by the second I/O trap; and
the second system management interrupt is received by a second system management interrupt handler of the second processor core; and
the second system management interrupt handler redirects the second transaction to the second direct media interface.

4. The information handling system of claim 1 , wherein the first LPC transaction is generated by a first keyboard control style handler associated with the first processor core.

5. The information handling system of claim 4 , wherein the first LPC transaction is received by a second keyboard control style handler associated with the service processor.

6. The information handling system of claim 1 , further comprising:
a system-on-a-chip device that includes the processor core, the I/O module, and the first direct media interface.

7. A method comprising:
receiving, at a first processor core, a first low pin count (LPC) transaction a first processor core;
sending the first LPC transaction for a service processor via a first direct media interface between the first processor core and a first input/output (I/O) module, and via a multi-master interface between the first I/O module and the service processor, such that the first LPC transaction is not transmitted via an LPC bus;
receiving the first LPC transaction at the first I/O module;
intercepting the first LPC transaction by a first I/O trap of the first I/O module;
generating a first system management interrupt in response to the first LPC transaction being intercepted by the first I/O trap;
receiving, by a first system management interrupt handler of the first processor core, the first system management interrupt; and
redirecting, by the first system management interrupt handler, the first transaction to the first direct media interface.

8. The method of claim 7 , further comprising:
receiving, at a second processor core, a second LPC transaction; and
sending the second LPC transaction for the service processor via a second direct media interface between the second processor core and a second I/O module, and via the multi-master interface to the service processor.

9. The method of claim 8 , further comprising:
receiving the second LPC transaction at the second I/O module;
intercepting the second LPC transaction by a second I/O trap of the second I/O module, such that the second LPC transaction is not transmitted via an LPC bus;
generating a second system management interrupt in response to the second LPC transaction being intercepted by the second I/O trap;
receiving, by a second system management interrupt handler of the second processor core, the second system management interrupt; and
redirecting, by the second system management interrupt handler, the second transaction to the second direct media interface.

10. The method of claim 7 , wherein the first LPC transaction is generated by a first keyboard control style handler associated with the first processor core.

11. The method of claim 10 , wherein the first LPC transaction is received by a second keyboard control style handler associated with the service processor.

12. A non-transitory computer-readable medium including code for carrying out a method, the method comprising:
receiving, at a first processor core, a first low pin count (LPC) transaction;
sending the first LPC transaction for a service processor via a first direct media interface between the first processor core and a first input/output (I/O) module, and via a multi-master interface between the first I/O module and the service processor, such that the first LPC transaction is not transmitted via an LPC bus;
receiving the first LPC transaction at the first I/O module;
intercepting the first LPC transaction by a first I/O trap of the first I/O module;
generating a first system management interrupt in response to the first LPC transaction being intercepted by the first I/O trap
receiving, by a first system management interrupt handler of the first processor core, the first system management interrupt; and
redirecting, by the first system management interrupt handler, the first transaction to the first direct media interface.

Assignees

• Butcher Wade A
• Holmberg Richard L
• Dell Products Lp

Inventors

• Butcher Wade A
• Holmberg Richard L

Classifications

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title