Predictive fetching and decoding for selected instructions

Patent metadata

Field	Value
Publication number	US-9619230-B2
Application number	US-201313931656-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.

First claim

What is claimed is:

1. A computer program product for facilitating processing within a processing environment, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising:
predicting that a selected instruction is to execute in a pipelined processor, the pipelined processor having a plurality of stages of processing including an execute stage, and the selected instruction having a first privilege level and one or more other instructions executing in the pipelined processor having a second privilege level different from the first privilege level;
based on predicting the selected instruction is to execute, predicting an entry address for the selected instruction and operating state associated therewith, the entry address indicating a location at which an instruction is to be fetched based on the selected instruction, and the operating state comprising a predicted privilege level for the instruction at the entry address;
storing the predicted operating state in a data structure coupled to a decode unit of the processing environment;
based on predicting the entry address, fetching the instruction at the entry address prior to the selected instruction reaching the execute stage; and
initiating decoding of the fetched instruction based on the predicted operating state, the decode unit to decode the fetched instruction based on the predicted operating state.

2. The computer program product of claim 1 , wherein the method further comprises executing the selected instruction, wherein the executing comprises:
updating a non-speculative operating state of the selected instruction based on executing the selected instruction;
comparing the non-speculative operating state with the predicted operating state; and
based on the comparing indicating a discrepancy, performing recovery.

3. The computer program product of claim 2 , wherein the performing recovery comprises:
performing a flush of the pipelined processor, the performing the flush providing a new fetch address and new speculative operating state;
based on performing the flush, initiating a fetch of an instruction at the new fetch address; and
processing the instruction fetched at the new fetch address based on the new speculative operating state.

4. The computer program product of claim 1 , wherein the method further comprises placing a return address for the selected instruction in an entry within a data structure, the return address to indicate an address to which processing is to return.

5. The computer program product of claim 4 , wherein the method further comprises including within the entry at least one of operating state for the return address and an indicator of a creator of the entry.

6. The computer program product of claim 1 , wherein the predicting the entry address comprises predicting the entry address based on one of a fixed value, a value in a register, or a cached value.

7. The computer program product of claim 1 , wherein the predicting comprises using branch prediction logic to predict that the selected instruction is to execute.

8. The computer program product of claim 1 , wherein the predicting the operating state comprises predicting a privilege level for the instruction at the entry address, the predicting the privilege level comprising predicting the privilege level based on one or more parameters associated with the selected instruction.

9. The computer program product of claim 1 , wherein the selected instruction comprises one of a system call instruction, a hypervisor call instruction or an asynchronous interrupt.

10. A computer system for facilitating processing within a processing environment, the computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
predicting that a selected instruction is to execute in a pipelined processor, the pipelined processor having a plurality of stages of processing including an execute stage, and the selected instruction having a first privilege level and one or more other instructions executing in the pipelined processor having a second privilege level different from the first privilege level;
based on predicting the selected instruction is to execute, predicting an entry address for the selected instruction and operating state associated therewith, the entry address indicating a location at which an instruction is to be fetched based on the selected instruction, and the operating state comprising a predicted privilege level for the instruction at the entry address;
storing the predicted operating state in a data structure coupled to a decode unit of the processing environment;
based on predicting the entry address, fetching the instruction at the entry address prior to the selected instruction reaching the execute stage; and
initiating decoding of the fetched instruction based on the predicted operating state, the decode unit to decode the fetched instruction based on the predicted operating state.

11. The computer system of claim 10 , wherein the method further comprises executing the selected instruction, wherein the executing comprises:
updating a non-speculative operating state of the selected instruction based on executing the selected instruction;
comparing the non-speculative operating state with the predicted operating state; and
based on the comparing indicating a discrepancy, performing recovery.

12. The computer system of claim 11 , wherein the performing recovery comprises:
performing a flush of the pipelined processor, the performing the flush providing a new fetch address and new speculative operating state;
based on performing the flush, initiating a fetch of an instruction at the new fetch address; and
processing the instruction fetched at the new fetch address based on the new speculative operating state.

13. The computer system of claim 10 , wherein the method further comprises placing a return address for the selected instruction in an entry within a data structure, the return address to indicate an address to which processing is to return.

14. The computer system of claim 13 , wherein the method further comprises including within the entry at least one of operating state for the return address and an indicator of a creator of the entry.

15. The computer system of claim 10 , wherein the selected instruction comprises one of a system call instruction, a hypervisor call instruction or an asynchronous interrupt.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Salapura Valentina

Classifications

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3806

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title