Apparatus and method for handling exception events

Patent metadata

Field	Value
Publication number	US-9104425-B2
Application number	US-201414149141-A
Country	US
Kind code	B2
Filing date	Jan 7, 2014
Priority date	Mar 15, 2010
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35 . When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4 . When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

First claim

I claim:

1. A data processing apparatus comprising:
processing circuitry configured to process data in one of a plurality of exception states including a base level exception state and at least one further level exception state;
a base level stack pointer register for storing a base level stack pointer indicating the location within a memory of a base level stack data store;
at least one further level stack pointer register for storing at least one further level stack pointer…

Assignees

• Advanced Risc Mach Ltd

Inventors

• Grisenthwaite Richard Roy

Classifications

• G06F9/30189

  Physics · mapped topic

• G06F9/30134

  Physics · mapped topic

• G06F9/30101 Primary

  Physics · mapped topic

• G06F9/3861 Primary

  Physics · mapped topic

• G06F12/1491

  Physics · mapped topic