Differential interface for inter-device communication in a battery management and protection system

Patent metadata

Field	Value
Publication number	US-9614661-B2
Application number	US-201213442502-A
Country	US
Kind code	B2
Filing date	Apr 9, 2012
Priority date	Apr 9, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A multi-cell battery stack includes a microcontroller and a string of battery management and protection IC devices connected to one another in a daisy chain configuration. Each battery management and protection IC device can include a communication interface circuit includes pairs of differential input signal lines, receivers including respective current comparator circuits to receive differential signals on the differential input signal lines, and transmitters to provide outgoing differential signals on the differential input signal lines. A digital circuit block allows signals to pass between the receivers and transmitters.

First claim

What is claimed is:

1. A battery management and protection integrated circuit comprising a communication interface circuit that comprises:
a first pair of differential input signal lines;
a first receiver comprising a first current comparator circuit to receive incoming differential signals on the first pair of differential input signal lines;
a first transmitter to provide outgoing differential signals on the first pair of differential input signal lines;
a second pair of differential input signal lines;
a second receiver comprising a second current comparator circuit to receive incoming differential signals on the second pair of differential input signal lines;
a second transmitter to provide outgoing differential signals on the second pair of differential input signal lines; and
a digital circuit block that allows signals to pass from the first receiver to the second transmitter and that allows signals to pass from the second receiver to the first transmitter,
wherein each of the first and second current comparator circuits includes:
class AB voltage output stages to generate current signals based on differential current input signals; and
current mirrors to transfer the current signals generated by the class AB voltage output stages to a summing node so as to provide a digital voltage output based on the differential input current.

2. The battery management and protection integrated circuit of claim 1 wherein current consumption by each of the first and second current comparator circuits is no greater than 5 μA.

3. A battery management and protection integrated circuit comprising a communication interface circuit that comprises:
a first pair of differential input signal lines;
a first receiver comprising a first current comparator circuit to receive incoming differential signals on the first pair of differential input signal lines;
a first transmitter to provide outgoing differential signals on the first pair of differential input signal lines;
a second pair of differential input signal lines;
a second receiver comprising a second current comparator circuit to receive incoming differential signals on the second pair of differential input signal lines;
a second transmitter to provide outgoing differential signals on the second pair of differential input signal lines; and
a digital circuit block that allows signals to pass from the first receiver to the second transmitter in a transparent manner and that allows signals to pass from the second receiver to the first transmitter in a transparent manner,
wherein each of the first and second transmitters includes a driver control portion and digital push/pull output drivers.

4. The battery management and protection integrated circuit of claim 3 wherein each of the first and second receivers is operable in an idle mode or in a transmission mode, and wherein a respective threshold of the respective first or second current comparator circuit is switchable depending on whether the respective first or second receiver is operating in the idle mode or transmission mode.

5. The battery management and protection integrated circuit of claim 4 wherein a first threshold value is used during the transmission mode and a second threshold value, having a magnitude at least five times as great as a magnitude of the first threshold value, is used during the idle mode.

6. The battery management and protection integrated circuit of claim 4 wherein a first threshold value is used during the transmission mode and a second threshold value having a greater magnitude is used during the idle mode.

7. The battery management and protection integrated circuit of claim 6 wherein the second threshold value is at least 750 mV.

8. The battery management and protection integrated circuit of claim 4 wherein the respective threshold of the respective first or second current comparator circuit is based on a signal from the digital circuit block.

9. The battery management and protection integrated circuit of claim 3 wherein the digital circuit block is operable to provide a first enable/disable signal to turn on/off the first receiver and the first transmitter and to provide as second enable/disable signal to turn on/off the second receiver and the second transmitter.

10. The battery management and protection integrated circuit of claim 3 wherein the push/pull output drivers in the second transmitter are activated when the first receiver detects beginning of a data transmission.

11. The apparatus of claim 10 wherein the push/pull output drivers in the first transmitter are activated when the second receiver detects beginning of a data transmission.

Assignees

• Roeper Wolfgang
• Ahlendorf Hendrik
• Schmidt Friedemann
• Atmel Corp

Inventors

• Roeper Wolfgang
• Ahlendorf Hendrik
• Schmidt Friedemann

Classifications

• H02J7/52

  for charge balancing, e.g. equalisation of charge between batteries · CPC title

• Y10T307/685

  Cross-Sectional Technologies · mapped topic

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/02

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H04L25/0282

  Provision for current-mode coupling · CPC title