System and method for deskewing output clock signals

Patent metadata

Field	Value
Publication number	US-9614508-B1
Application number	US-201514958701-A
Country	US
Kind code	B1
Filing date	Dec 3, 2015
Priority date	Dec 3, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A clock generator having deskewed outputs signals wherein a transit time of each of a plurality of traces coupled to the clock generator outputs are determined and the longest trace is identified as the trace having the longest transit time. A time delay is then added to an output clock signal at each of the clock generator outputs that are not coupled to the longest trace. The addition of the time delay for each of the clock generator outputs is effective in automatically deskewing the clock generator outputs.

First claim

What is claimed is:

1. A method for deskewing output clock signals, the method comprising:
determining, at a clock generator, a transit time of each of a plurality of traces, each of the plurality of traces coupled between one of a plurality of clock generator outputs and one of a plurality of clock receivers;
determining a longest transit time of the transit times of each of the plurality of traces;
determining a difference between the longest transit time and the transit time of each of the plurality of traces to identify a time delay for each of the plurality of clock generator outputs; and
adding the time delay for each of the plurality of clock generator outputs to a output clock signal transmitted from each of the plurality of clock generator outputs.

2. The method of claim 1 , wherein the transit time of each of the plurality of traces is approximately equal to one half of a round-trip transit time of a signal transmitted on the trace between the clock generator output and the clock receiver.

3. The method of claim 1 , wherein determining, at a clock generator, a transit time of each of a plurality of traces further comprises:
transmitting a signal on each of the plurality of clock generator outputs;
measuring a time required for a reflected signal resulting from the signal transmitted on each of the plurality clock generator outputs to reach a first voltage level;
measuring a time required for the reflected signal to reach a second voltage level; and
calculating a difference between the time required for the reflected signal to reach the first voltage level and the time required for the reflected signal to reach the second voltage level to determine a transit time for each of the plurality of traces.

4. The method of claim 3 , wherein the first voltage level is lower than the second voltage level.

5. The method of claim 3 , wherein the first voltage level is equal to about 20% of a voltage of the transmitted signal.

6. The method of claim 3 , wherein the second voltage level is equal to about 80% of a voltage of the transmitted signal.

7. The method of claim 3 , wherein measuring a time required for a reflected signal resulting from the signal transmitted on each of the plurality clock generator outputs to reach a first voltage level further comprises:
receiving the reflected signal at an input of a first buffer, the first buffer having a voltage threshold substantially equal to the first voltage level; and
detecting a rising edge at an output of the first buffer to measure the time required for the reflected signal to reach the first voltage level.

8. The method of claim 3 , wherein measuring the time required for a reflected signal to reach a second voltage level further comprises:
receiving the reflected signal at an input of a second buffer, the second buffer having a voltage threshold substantially equal to the second voltage level; and
detecting a rising edge at an output of the second buffer to measure the time required for the reflected signal to reach the second voltage level.

9. The method of claim 1 , wherein adding the time delay for each of the plurality of clock generator outputs to a output clock signal transmitted from each of the plurality of clock generator outputs, further comprises, not adding the time delay to an output clock signal transmitted from the clock output coupled to the trace having the longest transit time.

10. The method of claim 1 , further comprising converting the transit time of each of the plurality of traces to a digital transit time for each of the plurality of traces prior to determining a longest transit time of the transit times of each of the plurality of traces.

11. A circuit for deskewing output signals of a clock generator, the circuit comprising:
a plurality of line length to digital converter circuits, each of the line length to digital converter circuits coupled to one of a plurality of clock generator outputs of a clock generator and each of the line length to digital converter circuits configured to determine a transit time of a trace coupled between a clock generator output of the plurality of clock generator outputs and one of a plurality of clock receivers;
a control circuit coupled to each of the plurality of line length to digital converter circuits, the control circuit configured to determine a longest transit time of the transit times determined by each of the line length to digital converter circuits and to determine a difference between the longest transit time and each determined transit time of a trace identify a time delay for each of the plurality of clock generator outputs; and
a plurality of digitally controlled delay elements, each of the plurality of digitally controlled delay elements coupled to the control circuit and to one of the plurality of clock generator outputs and each of the digitally controlled delay elements configured to receive the time delay for the clock generator output that the digitally controlled delay element is coupled to from the control circuit and to add the received time delay for the clock generator output to an output clock signal transmitted from the clock generator output.

12. The circuit of claim 11 , wherein the transit time of a traces is approximately equal to one half of a transit time of a signal transmitted on the trace between the clock generator output and the clock receiver.

13. The circuit of claim 11 , wherein each of the plurality of line length to digital converter circuits are further configured to measure a time required for a reflected signal on the clock generator output to reach a first voltage level, measure a time required for the reflected signal to reach a second voltage level and calculate a difference between the time required for the reflected signal to reach the first voltage level and the time required for the reflected signal to reach a second voltage level to determine a transit time for the trace coupled to the clock generator output.

14. The circuit of claim 13 , wherein the first voltage level is equal to about 20% of a voltage of the transmitted signal.

15. The circuit of claim 13 , wherein the second voltage is equal to about 80% of a voltage of the transmitted signal.

16. The circuit of claim 13 , wherein each of the plurality of line length to digital converter circuits further comprises:
a first buffer configured to receive the reflected signal, wherein the first buffer comprises a voltage threshold substantially equal to the first voltage level; and
a second buffer configured to receive the reflected signal, wherein the second buffer comprises a voltage threshold substantially equal to the second voltage level.

17. The circuit of claim 16 , wherein each of the plurality of line length to digital converter circuits further comprises a time to digital converter circuit configured to detect a rising edge at an output of the first buffer to measure the time required for the reflected signal to reach the first voltage level and to detect a rising edge at an output of the second buffer to measure the time required for the reflected signal to reach the second voltage level.

18. The circuit of claim 17 , wherein the time to digital converter is further configured to convert a transit time equal to the difference between the time required for the reflected signal to reach the first voltage level and the time required for the reflected signal to reach the second voltage level to a digital transit time for the trace coupled to the clock generator output.

19. The circuit of claim 11 , wherein

Assignees

• Integrated Device Tech

Inventors

• Bal Jagdeep
• Poitras Louis F

Classifications

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/131

  Digitally controlled · CPC title