Apparatus and methods for chopping ripple reduction in amplifiers

Patent metadata

Field	Value
Publication number	US-9614481-B2
Application number	US-201514675087-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Apparatus and methods for digitally-assisted feedback offset correction are provided herein. In certain configurations, an amplifier includes amplification circuitry for providing amplification to an input signal and chopping circuitry for compensating for an input offset voltage of the amplifier. Additionally, the amplifier further includes a digitally-assisted feedback offset correction circuit, which includes a chopping ripple detection circuit, a feedback-path chopping circuit, a digital correction control circuit, and an offset correction circuit. The chopping ripple detection circuit generates a detected ripple signal based on detecting an output ripple of the amplifier. Additionally, the feedback-path chopping circuit demodulates the detected ripple signal using the amplifier's chopping clock signal. The digital correction control circuit receives the demodulated ripple signal, which the digital correction control circuit uses to control a value of a digital offset control signal that controls an amount of input offset correction provided by the offset correction circuit.

First claim

What is claimed is:

1. An amplifier comprising:
amplification circuitry configured to generate an output signal based on amplifying a differential input voltage signal;
chopping circuitry configured to provide chopping to the differential input voltage signal; and
a feedback offset correction circuit comprising:
a chopping ripple detection circuit configured to generate a detected ripple signal based on detecting a chopping ripple of the amplifier associated with the chopping;
a feedback-path chopping circuit configured to generate a demodulated ripple signal based on chopping the detected ripple signal;
a digital correction control circuit configured to generate a digital correction control signal based on the demodulated ripple signal, wherein the digital correction control circuit is controlled by a control clock signal having a frequency that changes with an operating mode of the amplifier; and
an offset correction circuit configured to correct for an input offset voltage of the amplification circuitry based on a value of the digital correction control signal.

2. An amplifier comprising:
amplification circuitry configured to generate an output signal based on amplifying a differential input voltage signal;
chopping circuitry configured to provide chopping to the differential input voltage signal; and
a feedback offset correction circuit comprising:
a chopping ripple detection circuit configured to generate a detected ripple signal based on detecting a chopping ripple of the amplifier associated with the chopping, wherein the chopping ripple detection circuit comprises one or more AC-coupling capacitors and a transconductance amplification stage, wherein the AC-coupling capacitors are configured to provide coupling of the chopping ripple to an input of the transconductance amplification stage;
a feedback-path chopping circuit configured to generate a demodulated ripple signal based on chopping the detected ripple signal;
a digital correction control circuit configured to generate a digital correction control signal based on the demodulated ripple signal, wherein the digital correction control circuit is controlled by a control clock signal; and

an offset correction circuit configured to correct for an input offset voltage of the amplification circuitry based on a value of the digital correction control signal.

3. The amplifier of claim 1 , wherein the feedback offset correction circuit further comprises a clock rate control circuit configured to operate a frequency of the control clock signal at higher frequency in a calibration mode relative to a normal operating mode.

4. The amplifier of claim 3 , further comprising a multiplexer configured to provide the differential input voltage signal to the amplification circuitry in the normal operating mode and to provide a differential input voltage of about 0 V to the amplification circuitry in the calibration mode.

5. The amplifier of claim 3 , wherein the digital correction control circuit comprises a successive approximation register configured to operate during the calibration mode.

6. The amplifier of claim 1 , further comprising a non-inverting input voltage terminal, an inverting input voltage terminal, and an output voltage terminal, wherein the amplifier is configured to receive the differential input voltage signal between the non-inverting input voltage terminal and the inverting input voltage terminal.

7. The amplifier of claim 6 , further comprising a feedback circuit electrically connected between the output voltage terminal and the inverting input voltage terminal, wherein the chopping ripple detection circuit includes an input electrically connected to the inverting input voltage terminal.

8. The amplifier of claim 6 , wherein the chopping ripple detection circuit includes an input electrically connected to the output voltage terminal.

9. The amplifier of claim 2 wherein the feedback offset correction circuit has a loop bandwidth of less than 100 Hz.

10. The amplifier of claim 1 , wherein a frequency of the control clock signal is less than 100 Hz when the amplification circuitry is amplifying the differential input voltage signal such that the feedback offset correction circuit operates with narrow bandwidth.

11. The amplifier of claim 2 wherein the offset correction circuit comprises a current-steering digital-to-analog converter (DAC), wherein the amplification circuitry comprises an input transistor differential pair including a first transistor and a second transistor, wherein the current-steering DAC is configured to adjust a bias current of the first transistor relative to a bias current of the second transistor based on the value of the digital correction control signal.

12. The amplifier of claim 2 wherein the offset correction circuit comprises a voltage DAC, wherein the amplification circuitry comprises an input amplification stage and an auxiliary amplification stage electrically connected in parallel with one another, wherein the voltage DAC is configured to control an input voltage to the auxiliary amplification stage based on the value of the digital correction control signal.

13. The amplifier of claim 2 wherein the digital correction control circuit comprises a counter configured to control the value of the digital correction control signal and a comparator configured to control an input to the counter based on the demodulated ripple signal.

14. The amplifier of claim 2 wherein the chopping circuitry comprises an input chopping circuit and an output chopping circuit, wherein at least one amplification stage of the amplification circuitry is electrically connected between the input chopping circuit and the output chopping circuit.

15. The amplifier of claim 2 , further comprising a feedback circuit electrically connected between an output voltage terminal and an inverting input voltage terminal of the amplifier, wherein the chopping ripple detection circuit includes an input electrically connected to the inverting input voltage terminal.

16. A method of input offset correction for a chopper amplifier, the method comprising:
amplifying a differential input voltage signal using amplification circuitry;
chopping the differential input voltage signal using chopping circuitry;
generating a detected ripple signal based on detecting a chopping ripple associated with the chopping;
generating a demodulated ripple signal based on demodulating the detected ripple signal;
generating a digital correction control signal based on the demodulated ripple signal and a control clock signal;
correcting an input offset voltage of the amplification circuitry based on a value of the digital correction control signal; and
changing a frequency of the control clock signal based on an operating mode of the chopper amplifier.

17. The method of claim 16 , further comprising operating a frequency of the control clock signal at less than 100 Hz when amplifying the differential input voltage signal.

18. The method of claim 16 , further comprising correcting the input offset voltage of the amplification circuitry using a loop bandwidth of less than 100 Hz.

19. The method of claim 16 , further comprising operating a frequency of the control clock signal at a higher frequency in a calibration mode of the chopper amplifier relative to a normal operating mode of the chopper amplifier.

20. The method of claim 16 , further comprising:
integrating the demodulated ripple signal to generate an integrated signal;
performing a plurality of comparison opera

Assignees

• Analog Devices Inc

Inventors

• Ivanov Evgueni

Classifications

• H03F2203/45044

  One or more switches are opened or closed to balance the dif amp to reduce the offset of the dif amp · CPC title

• H03F3/45977 Primary

  using switching means, e.g. sample and hold · CPC title

• H03F2203/7212

  the gated amplifier being switched on or off by switching off or on a feedback control loop of the amplifier · CPC title

• H03F2200/249

  A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch · CPC title

• H03F2203/45212

  the differential amplifier being designed to have a reduced offset · CPC title