High performance digital to analog converter

Patent metadata

Field	Value
Publication number	US-9728261-B2
Application number	US-201715448813-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Mar 14, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

First claim

What is claimed is:

1. A method of operating an amplification block of a digital to analog converter comprising an amplifier, the method comprising:
receiving, at a first input terminal of the amplifier, a first analog value;
providing, at an output terminal of the amplifier, a second analog value amplified by an amplification factor with respect to the first analog value, the amplification block comprising a first capacitive element and a second capacitive element coupled to the output terminal of the amplifier, the amplification factor being determined by the first capacitive element and the second capacitive element; and
recovering an operative charge at a second input terminal of the amplifier, and based thereon, the second analog value to the output terminal of the amplifier.

2. The method of claim 1 , wherein the first input terminal and the second input terminal of the amplification block comprise a non-inverting input terminal and an inverting input terminal, respectively.

3. The method of claim 1 , wherein the first capacitive element comprises a first terminal and a second terminal coupled to the output terminal and the second input terminal of the amplifier, respectively, and wherein the second capacitive element comprises a first terminal and a second terminal coupled to the second terminal of the first capacitive element and to a reference potential, respectively.

4. The method of claim 3 , wherein the amplification block further comprises a further first capacitive element and a further second capacitive element, a first terminal of the further first capacitive element being controllably coupled to one of the output terminal of the amplifier or the reference potential, a first terminal of the further second capacitive element being coupled to a second terminal of the further first capacitive element, and a second terminal of the further second capacitive element being coupled to the reference potential.

5. The method of claim 4 , wherein the recovering comprises:
charging the first terminal of the further first capacitive element to a recovery charge; and
coupling the first terminal of the further second capacitive element charged at the recovery charge to the first terminal of the second capacitive element, wherein the charge at the first terminal of the further second capacitive element and the charge at the first terminal of the second capacitive element are equalized to the operative charge in response to the coupling.

6. The method of claim 5 , wherein charging the first terminal of the further first capacitive element to the recovery charge comprises:
first coupling the first terminal of the further first capacitive element and the first terminal of the further second capacitive element to the reference potential, wherein the first terminal of the further second capacitive element is charged to a reference charge in response to the coupling;
decoupling, subsequent to the first coupling, the first terminal of the further first capacitive element and the first terminal of the further second capacitive element from the reference potential; and
second coupling the first terminal of the further first capacitive element to the output terminal of the amplification block, the first terminal of the further second capacitive element being charged to the recovery charge from the reference potential in response to the second coupling.

7. A method of operating an amplification block of a digital to analog converter comprising an amplifier, the method comprising:
receiving, at a first input terminal of the amplifier, a first analog value based on a digital value;
providing, at an output terminal of the amplifier, a second analog value amplified by an amplification factor with respect to the first analog value, the amplification block further comprising a first capacitive element having a first terminal and a second terminal coupled to the output terminal and to a second input terminal of the amplifier, respectively, the amplification block further comprising a second capacitive element having a first terminal and a second terminal coupled to the second terminal of the first capacitive element and a reference terminal, respectively; and
recovering, at each of a plurality of time periods, an operative charge at the first terminal of the second capacitive element, and based thereon, the second analog value to the output terminal of the amplifier.

8. The method of claim 7 , wherein the recovering comprises:
charging a first terminal of a further first capacitive element to a recovery charge; and
coupling a first terminal of a further second capacitive element charged at the recovery charge to the first terminal of the second capacitive element, wherein, in response to the coupling, the charge at the first terminal of the further second capacitive element and the charge at the first terminal of the second capacitive element are equalized to the operative charge, the first terminal of the further second capacitive element being coupled to a second terminal of the further first capacitive element and a second terminal of the further second capacitive element being coupled to the reference terminal.

9. The method of claim 8 , wherein charging the first terminal of the further first capacitive element to the recovery charge further comprises:
coupling the first terminal of the further first capacitive element and the first terminal of the further second capacitive element to the reference terminal, wherein, in response to the coupling, the first terminal of the further second capacitive element is charged to a reference charge; and
coupling the first terminal of the further first capacitive element to the output terminal of the amplifier, wherein, in response to the coupling, the first terminal of the further second capacitive element is charged to the recovery charge from the reference terminal.

10. The method of claim 7 , wherein the first input terminal and the second input terminal of the amplifier comprise a non-inverting input and an inverting input of the amplifier, respectively.

11. The method of claim 7 , wherein the amplification factor is determined by the first capacitive element and the second capacitive element.

12. A method of operating an amplification block of a digital to analog converter comprising a first capacitive network having a first node coupled to an output terminal of an amplifier and a second node coupled to a first input terminal of the amplifier, and a second capacitive network having a first node controllably coupled to the output terminal of the amplifier and a second node controllably coupled to the first input terminal of the amplifier, the method comprising:
first coupling the first node and the second node of the second capacitive network to a reference terminal to charge the first node and the second node of the second capacitive network to a reference voltage;
first decoupling, after the first coupling, the first node and the second node of the second capacitive network from the reference terminal;
second coupling the first node of the second capacitive network to the output terminal of the amplifier to charge the first node of the second capacitive network to a recovery charge; and
third coupling the second node of the second capacitive network, at the recovery charge, to the first input terminal of the amplifier, wherein a charge at the second node of the second capacitive network and a charge at the second node of the first capacitive network are equalized to an operative charge in response to the third coupling.

13. The method of claim 12 , further comprising:
receiving, at a second input terminal of the

Assignees

• St Microelectronics Srl

Inventors

• Conte Antonino
• Giaquinta Maria

Classifications

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H03F2203/45332

  the AAC comprising one or more capacitors as feedback circuit elements · CPC title

• H03F2203/45546

  the IC comprising one or more capacitors feedback coupled to the IC · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title