Low resistivity damascene interconnect

Patent metadata

Field	Value
Publication number	US-9613907-B2
Application number	US-201514809266-A
Country	US
Kind code	B2
Filing date	Jul 26, 2015
Priority date	Jul 29, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

First claim

What is claimed is:

1. A low resistivity damascene interconnect, comprising:
a dielectric material having a trench formed therein;
a first liner material arranged along sidewalls of the trench but not a bottom surface of the trench;
a second liner material, different from the first liner material, arranged along a bottom surface of the trench but not contacting or arranged along sidewalls of the trench; and
a conductive material deposited on and contacting the first and second liner materials and filling the trench,
wherein the first liner material has a relatively low wettability with respect to the conductive material,
wherein the second liner material has a relatively high wettability with respect to the conductive material,
wherein the conductive material has a preferred metal grain orientation that is a crystalline [111] structure oriented in a direction that is transverse to a direction of electron transport through the interconnect, and
wherein a pitch dimension of the interconnect is less than approximately 30 nm.

2. An interconnect according to claim 1 , wherein the conductive material is copper (Cu), aluminum (Al), gold (Au), or silver (Ag).

3. An interconnect according to claim 1 , wherein the first liner material is tantalum (Ta), and wherein the second liner material is Ruthenium (Ru).

4. An interconnect according to claim 1 , wherein the first liner material and the second liner material comprise thicknesses that are different from each other.

5. An interconnect according to claim 1 , wherein the first liner material is arranged between the second liner material and sidewalls of the trench.

6. An interconnect according to claim 4 , wherein a thickness of the first liner material is approximately 0.5 nm and wherein a thickness of the second liner material is approximately between 1.5 nm and 2 nm.

7. An interconnect according to claim 1 , wherein a thickness of the first liner material is thinner than a thickness of the second liner material.

8. An interconnect according to claim 7 , wherein a thickness of the second liner material is between approximately 1.5 nm and approximately 2 nm.

9. An interconnect according to claim 1 , further comprising a barrier layer arranged along the bottom and sidewalls of the trench between the dielectric and the respective first and second liner materials.

10. An interconnect according to claim 1 , wherein a pitch dimension of the interconnect is less than about 15 nm.

11. A method of forming a damascene interconnect, the method comprising:
forming a trench in an inter-layer dielectric (ILD);
conformally depositing a diffusion barrier layer along sidewalls and a bottom surface of the trench;
conformally depositing a first liner layer comprising a first liner material on the diffusion barrier layer;
removing the first liner layer from the diffusion barrier layer except along sidewalls of the trench;
forming a second liner layer comprising a second liner material along a bottom surface of the trench but not along sidewalls of the trench after removing the first liner layer from the bottom surface of the trench, such that the first liner material is arranged between the second liner material and sidewalls of the trench;
depositing a conductive seed layer of a conductive material on the first and second liner layers; and
filling the trench with the conductive material overlying the conductive seed layer,
wherein the first liner material is selected having a relatively low wettability with respect to the conductive material,
wherein the second liner material is selected having a relatively high wettability with respect to the conductive material,
wherein the conductive material has a preferred metal grain orientation that is a crystalline [111] structure oriented in a direction that is transverse to a direction of electron transport through the interconnect, and
wherein a pitch dimension of the interconnect is less than approximately 30 nm.

12. The method of claim 11 , further comprising performing a chemical mechanical planarization (CMP) process after filling the trench with the conductive material to form the damascene interconnect structure.

13. The method of claim 11 , wherein the conductive material is copper (Cu), wherein the first liner material is tantalum (Ta), and wherein the second liner material is ruthenium (Ru).

14. The method of claim 11 , wherein forming the second liner layer comprises directionally depositing the second liner material on horizontal surfaces of the ILD and performing an etch or cleaning process to remove any second liner material inadvertently deposited on vertical surfaces of the trench.

15. The method of claim 11 , further comprising forming multiple damascene interconnects and wherein the damascene interconnects are formed at a same integration level or a different integration level from other damascene interconnects formed by the same method.

16. A damascene interconnect comprising:
a dielectric having a trench formed therein;
a first liner material arranged along sidewalls of the trench but not a bottom surface of the trench;
a second liner material arranged along the bottom surface of the trench but not contacting or arranged along the sidewalls of the trench,
wherein the second liner material is different from the first liner material,
wherein the first liner material has relatively low wettability with respect to the conductive material, and
wherein the second liner material has relatively higher wettability with respect to the conductive material; and

a conductive material filling the trench,
wherein the conductive material has a preferred grain orientation that is transverse to a direction of electron transport through the interconnect, said transverse preferred grain orientation resulting from the difference between the first and second liner materials and a minimization of an energy of a free surface of the conductive material, and
wherein a pitch dimension of the interconnect is less than approximately 15 nm.

17. The interconnect of claim 16 , wherein the first liner material is tantalum (Ta), wherein the second liner material is Ruthenium (Ru), and wherein a thickness of the first liner material is thinner than a thickness of the second liner material.

18. The interconnect of claim 17 , wherein a thickness of the second liner material is between approximately 1.5 nm and approximately 2 nm.

19. The interconnect of claim 16 , wherein the interconnect is formed from a single damascene interconnect process for a conductive line.

20. The interconnect of claim 16 , wherein the interconnect is formed at a same integration level or a different integration level than other damascene interconnects formed by the same method.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hegde Ganesh
• Rodder Mark S
• Kittl Jorge A
• Bowen Robert C

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/034

  bottomless barrier, adhesion or liner layers · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title