Encapsulated dies with enhanced thermal performance

Patent metadata

Field	Value
Publication number	US-9613831-B2
Application number	US-201514959129-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Mar 25, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

First claim

What is claimed is:

1. A method comprising:
attaching a plurality of flip chip dies on a top surface of a carrier;
applying a first mold compound over the top surface of the carrier to encapsulate the plurality of flip chip dies;
thinning the first mold compound down to expose substrates of the plurality of flip chip dies;
etching away substantially the entire substrate of each of the plurality of flip chip dies with an etchant to provide an etched flip chip die that has an exposed surface at the bottom of a cavity; and
applying a second mold compound to substantially fill each cavity and directly contact the exposed surface of each etched flip chip die.

2. The method of claim 1 wherein the carrier is one of a group consisting of a laminate, a wafer level fan out (WLFO) carrier, a lead frame, and a ceramic carrier.

3. The method of claim 1 wherein the first mold compound is an organic epoxy resin system.

4. The method of claim 1 wherein a thickness of the substrate of each of the plurality of flip chip dies is 150-500 μm.

5. The method of claim 1 wherein the first mold compound is resistant to the etchant.

6. The method of claim 1 wherein the exposed surface at the bottom of the cavity is a top surface of a device layer of each etched flip chip die.

7. The method of claim 6 wherein the device layer includes at least one of a group consisting of diodes, transistors, mechanical switches, and resonators.

8. The method of claim 6 wherein a thickness of the device layer is 4-7 μm.

9. The method of claim 1 wherein the second mold compound has high thermal conductivity between 2.5 w/m·k and 10 w/m·k.

10. The method of claim 1 wherein the first mold compound is formed from a first material, and the second mold compound is formed from the first material.

11. The method of claim 1 wherein applying the first mold compound over the top surface of the carrier to encapsulate the plurality of flip chip dies is provided by sheet molding.

12. The method of claim 1 wherein applying the first mold compound over the top surface of the carrier to encapsulate the plurality of flip chip dies is provided by overmolding.

13. The method of claim 1 wherein applying the first mold compound over the top surface of the carrier to encapsulate the plurality of flip chip dies is provided by compression molding.

14. The method of claim 1 wherein applying the second mold compound to substantially fill each cavity is provided by sheet molding.

15. The method of claim 1 wherein applying the second mold compound to substantially fill each cavity is provided by overmolding.

16. The method of claim 1 wherein applying the second mold compound to substantially fill each cavity is provided by compression molding.

17. The method of claim 1 further comprising applying a protective coating over a bottom surface of the carrier.

18. The method of claim 17 further comprising removing the protective coating over the bottom surface of the carrier.

19. The method of claim 17 wherein the protective coating is one of a group consisting of a chemical resistant tape, a liquid protective coating, and a rigid protective carrier.

20. The method of claim 1 further comprising planarizing a top surface of the second mold compound.

21. The method of claim 1 wherein the first mold compound and the second mold compound are formed from different materials.

22. The method of claim 21 wherein the second mold compound has a thermal conductivity between 2.5 w/m·k and 10 w/m·k.

23. The method of claim 21 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.

24. The method of claim 22 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.

25. The method of claim 21 wherein the first mold compound is resistant to the etchant.

26. The method of claim 1 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.

27. The method of claim 1 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.

Assignees

• Rf Micro Devices Inc
• Qorvo Us Inc

Inventors

• Morris Thomas Scott
• Jandzinski David
• Parker Stephen
• Chadwick Jon
• Costa Julio C

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title