Triple patterning NAND flash memory

Patent metadata

Field	Value
Publication number	US-9613806-B2
Application number	US-201314018236-A
Country	US
Kind code	B2
Filing date	Sep 4, 2013
Priority date	Sep 4, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

First claim

It is claimed:

1. A method of forming a hard mask layer comprising:
forming a plurality of mandrels that have a lateral dimension D which is defined by a photolithographic process and which are separated by spaces having a lateral dimension equal to D;
subsequently forming sidewall spacers of a first material along and in direct contact with sides of the mandrels, gaps between neighboring sidewall spacers having a lateral dimension approximately equal to D/3;
subsequently depositing a first hard mask layer of a second material to completely fill the gaps between the sidewall spacers with the second material;
subsequently etching the plurality of mandrels to expose sides of the sidewall spacers;
subsequently depositing a second hard mask layer of the second material to partially fill openings where the plurality of mandrels were etched, the second hard mask layer lying along and in direct contact with the sides of the sidewall spacers of the first material exposed by the etching;
subsequently etching back the second material of at least the second hard mask layer to leave first hard mask portions completely filling the gaps between sidewall spacers and second hard mask portions that extend along and in direct contact with the sidewall spacers on one side and are exposed on another side;
wherein both the first and second hard mask portions have lateral dimensions of approximately D/3 and spacing of approximately D/3; and
subsequently removing the sidewall spacers.

2. The method of claim 1 wherein an individual mandrel is formed of a lower layer of amorphous Silicon and an upper layer of Silicon Nitride.

3. The method of claim 2 wherein etching the plurality of mandrels removes the upper layer of Silicon Nitride from the plurality of mandrels while leaving the lower layer of amorphous Silicon substantially intact.

4. The method of claim 3 wherein the plurality of mandrels, and the sidewall spacers, are formed on a Silicon Nitride etch stop layer.

5. The method of claim 4 further comprising, subsequent to removing the sidewall spacers, etching through the Silicon Nitride etch stop layer according to a pattern established by the first and second hard mask portions.

6. The method of claim 1 wherein the first hard mask layer and the second hard mask layer are formed of amorphous Silicon.

7. The method of claim 1 wherein the sidewall spacers are formed of Silicon Dioxide.

8. The method of claim 1 wherein the plurality of mandrels consist of Silicon Nitride, the sidewall spacers are formed of Silicon Dioxide, the first hard mask layer and the second hard mask layer are formed of amorphous Silicon, and wherein a layer of amorphous Silicon directly underlies the plurality of mandrels and the sidewall spacers.

9. The method of claim 8 wherein etching the plurality of mandrels removes the plurality of mandrels to expose the layer of amorphous Silicon.

10. The method of claim 9 wherein the second hard mask layer is deposited directly on exposed areas of the layer of amorphous Silicon.

11. A method of forming an integrated circuit comprising:
forming a plurality of patterned portions using direct patterning photolithography;
subsequently forming sidewall spacers of a first material along and in direct contact with sidewalls of the plurality of patterned portions;
subsequently completely filling gaps between sidewalls of neighboring patterned portions with first hard mask portions of a second material that lie in direct contact with sidewall spacers on either side;
subsequently removing the plurality of patterned portions;
subsequently forming second hard mask portions of the second material in spaces where the plurality of patterned portions were removed, two second hard mask portions being formed in each space where an individual patterned portion was removed, each hard mask portion lying in direct contact with a sidewall spacer on one side;
wherein both the first and second hard mask portions have lateral dimensions of approximately D/3 and spacing of approximately D/3;
subsequently removing the sidewall spacers; and
subsequently using the first hard mask portions of the second material and the second hard mask portions of the second material to pattern one or more layers on a substrate.

12. The method of claim 11 wherein the patterned portions are formed of Silicon Nitride, or a combination of Silicon Nitride and amorphous Silicon.

13. The method of claim 12 wherein the sidewall spacers are formed of Silicon Dioxide.

14. The method of claim 13 wherein the first and second hard mask portions are formed of amorphous Silicon.

15. The method of claim 14 wherein a layer that directly underlies the sidewall spacers is formed of Silicon Dioxide.

16. The method of claim 11 wherein the plurality of patterned portions are formed having a lateral dimension D and wherein the first and second hard mask portions have a lateral dimension that is approximately one third of the lateral dimension D.

Assignees

• Sandisk Technologies Llc

Inventors

• Sel Jongsun
• Pham Tuan Duc
• Hong Mun Pyo

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic