Apparatus and method for drift cancellation in a memory

Patent metadata

Field	Value
Publication number	US-9613691-B2
Application number	US-201514671972-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

First claim

We claim:

1. An apparatus comprising:
a plurality of memory cells;
a bias logic coupled with at least one memory cell of the plurality, the bias logic to:
apply a first read voltage to the at least one memory cell; and
apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and

a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell.

2. The apparatus of claim 1 , wherein the first read voltage is to be applied before the second read voltage.

3. The apparatus of claim 1 , wherein the first and second read voltages are to be applied as first and second read pulses such that the first read pulse is to end before the second read pulse is to begin.

4. The apparatus of claim 3 , wherein the first read pulse has an amplitude which is sufficient to cancel drift in the at least one memory cell.

5. The apparatus of claim 3 , wherein the first read pulse has an amplitude which is greater than a SET threshold but lower than a RESET threshold.

6. The apparatus of claim 1 comprises:
a second circuit to pre-charge the word-line; and
a third circuit to increase voltage to a bit-line to select the at least one memory cell.

7. The apparatus of claim 6 , wherein the second circuit is to pre-charge the word-line prior to the first circuit is to float the word-line, and wherein the third circuit is to increase the voltage to the bit-line after the first circuit is to float the word-line.

8. The apparatus of claim 1 , wherein the plurality of memory cells are multi-level cells (MLCs) or single-level cells (SLCs).

9. The apparatus of claim 1 , wherein the plurality of memory cells exhibit reversible phase change from relatively amorphous phase to relatively crystalline phase.

10. The apparatus of claim 1 , wherein the plurality of memory cells are formed of a material that is operable to refresh at least one property of the material upon application of the first read voltage.

11. A system comprising:
a processor;
a memory coupled to the processor, the memory having:
an array of plurality of memory cells; and
a memory controller coupled to the array, the memory controller including:
a bias logic coupled with at least one memory cell of the plurality, the bias logic to:
apply a first read voltage to the at least one memory cell; and
apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and

a circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell; and

a wireless interface to allow the processor to communicate with another device.

12. The system of claim 11 , wherein the array of plurality of memory cells are formed of a material that is operable to refresh at least one property of the material upon application of the first read voltage.

13. The system of claim 11 , wherein the first and second read voltages are applied as first and second read pulses such that the first read pulse ends before the second read pulse begins.

14. A method comprising:
performing a first read operation to at least one memory cell; and
performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

15. The method of claim 14 , wherein performing the first read operation comprises:
pre-charging one of a word-line or a bit-line;
floating one of the pre-charged word-line or the pre-charged bit-line;
increasing voltage of one of the un-floating word-line or bit-line to select the at least one memory cell from a plurality of memory cells; and
applying a first read voltage to the selected at least one memory cell of a plurality of memory cells.

16. The method of claim 15 , wherein performing the second read operation comprises:
applying a second read voltage to the selected at least one memory cell without floating the word-line or the bit-line.

17. The method of claim 16 , wherein the first read voltage is higher than the second read voltage.

18. The method of claim 16 , wherein applying the first and second read voltages comprises applying first and second read pulses, respectively, such that the first read pulse ends before the second read pulse begins.

19. The method of claim 16 , wherein applying the first read pulse comprises applying a pulse having an amplitude sufficient to cancel drift in the at least one memory cell.

20. The method of claim 15 , wherein the memory cell is formed of a material that is operable to refresh at least one property of the material upon application of the first read voltage.

Assignees

• Intel Corp

Inventors

• Mantegazza Davide
• Damle Prashant S
• Pangal Kiran
• Belgal Hanmant P
• Pandey Abhinav

Classifications

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C2013/0052

  Read process characterized by the shape, e.g. form, length, amplitude of the read pulse · CPC title

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title