Isolating, at least in part, local row or column circuitry of memory cell before establishing voltage differential to permit reading of cell

Patent metadata

Field	Value
Publication number	US-9030906-B2
Application number	US-201213995230-A
Country	US
Kind code	B2
Filing date	Jun 6, 2012
Priority date	Jun 6, 2012
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.

First claim

What is claimed is:

1. An apparatus comprising:
local row circuitry that is local to a memory cell of a memory device;
local column circuitry that is local to the memory cell;
wherein one of the local row circuitry and the local column circuitry is to be electrically isolated, at least in part, from at least one remaining portion of the memory device during, at least in part, establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell, the read to occur subsequent to the establishing of the voltage differential;
also wherein:
if the one of the local row circuitry and the local column circuitry is the local row circuitry:
the at least one remaining portion of the memory device comprises global row circuitry and decode circuitry of the memory device; and
during the read of the memory cell, the local row circuitry is to be electrically coupled to the global row circuitry and the decode circuitry; and

if the one of the local row circuitry and the local column circuitry is the local column circuitry:
the at least one remaining portion of the memory device comprises global column circuitry and the decode circuitry of the memory device; and
during the read of the memory cell, the local column circuitry is to be electrically coupled to the global column circuitry and the decode circuitry.

2. The apparatus of 1 , wherein:
the memory device is comprised in a removable memory device that is capable of being removably coupled to a host via an interface of the host.

3. The apparatus of claim 1 , wherein:
the memory device is a non-volatile memory device.

4. An apparatus comprising:
local row circuitry that is local to a memory cell of a memory device;
local column circuitry that is local to the memory cell;
wherein one of the local row circuitry and the local column circuitry is to be electrically isolated, at least in part, from at least one remaining portion of the memory device during, at least in part, establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell, the read to occur subsequent to the establishing of the voltage differential;
also wherein:
prior to electrically isolating, at least in part, the one of the local row circuitry and the local column circuitry from the at least one remaining portion of the memory device, the one of the local row circuitry and local column circuitry is to have a voltage amplitude relative to the other of the local row circuitry and the local column circuitry that is less than the voltage differential; and
contemporaneous with the establishing of the voltage differential, the one of the local row circuitry and the local column circuitry is to be electrically isolated, at least in part, from the at least one remaining portion such that the one of the local row circuitry and the local column circuitry is electrically isolated, at least in part, from capacitance of the at least one remaining portion.

5. An apparatus comprising:
local row circuitry that is local to a memory cell of a memory device;
local column circuitry that is local to the memory cell;
wherein one of the local row circuitry and the local column circuitry is to be electrically isolated, at least in part, from at least one remaining portion of the memory device during, at least in part, establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell, the read to occur subsequent to the establishing of the voltage differential;
also wherein:
the memory cell is a phase change memory cell;
if the memory cell is in a set state:
prior to the establishing of the voltage differential, the memory cell is to be in a relatively high resistance state relative to a relatively low resistance state;
after the establishing of the voltage differential, the memory cell is to enter the relatively low resistance state, and thereafter, the memory cell is to return to the relatively high resistance state; and
during the read, the memory cell is to be in the relatively high resistance state while the at least one remaining portion is electrically coupled to the at least one remaining portion.

6. The apparatus of claim 5 , wherein:
during a voltage snap-back of the memory cell, the one of the local row circuitry and the local column circuitry is to be electrically de-coupled at least in part from the at least one remaining portion.

7. The apparatus of claim 5 , wherein:
if the memory cell is in a reset state:
prior to the establishing of the voltage differential, the memory cell is to be in the relatively high resistance state; and
after the establishing of the voltage differential, the memory cell is to remain in the relatively high resistance state.

8. A method comprising:
electrically isolating, at least in part, one of local row circuitry and low column circuitry from at least one remaining portion of a memory device during, at least in part, establishing of a voltage differential between the local row circuitry and the local column circuitry, the local row circuitry and the local column circuitry being local to a memory cell of the memory device, the voltage differential being to permit the memory cell to be read during a read of the memory cell, the read to occur subsequent to the establishing of the voltage differential;
also wherein:
if the one of the local row circuitry and the local column circuitry is the local row circuitry:
the at least one remaining portion of the memory device comprises global row circuitry and decode circuitry of the memory device; and
during the read of the memory cell, the local row circuitry is to be electrically coupled to the global row circuitry and the decode circuitry; and

if the one of the local row circuitry and the local column circuitry is the local column circuitry:
the at least one remaining portion of the memory device comprises global column circuitry and the decode circuitry of the memory device; and
during the read of the memory cell, the local column circuitry is to be electrically coupled to the global column circuitry and the decode circuitry.

9. The method of claim 8 , wherein:
prior to the electrically isolating, at least in part, of the one of the local row circuitry and the local column circuitry from the at least one remaining portion of the memory device, the one of the local row circuitry and local column circuitry is to have a voltage amplitude relative to the other of the local row circuitry and the local column circuitry that is less than the voltage differential; and
contemporaneous with the establishing of the voltage differential, the one of the local row circuitry and the local column circuitry is to be electrically isolated, at least in part, from the at least one remaining portion such that the one of the local row circuitry and the local column circuitry is electrically isolated, at least in part, from capacitance of the at least one remaining portion.

10. The method of claim 8 , wherein:
the memory cell is a phase change memory cell;
if the memory cell is in a set state:
prior to the establishing of the voltage differential, the memory cell is to be in a relatively high resistance state relative to a relatively low resistance state;
after the establishing of the voltage differential, the memory cell is to enter the relatively low resistance state, and thereafter, the memory cell is to return to the relatively high resistance state; and
during the read, the

Assignees

• Rivers Doyle
• Damle Prashant S
• Zeng Raymond W
• Intel Corp

Inventors

• Rivers Doyle
• Damle Prashant S
• Zeng Raymond W

Classifications

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title