Synchronization mechanisms for high-integrity computing

Patent metadata

Field	Value
Publication number	US-9612985-B1
Application number	US-201414462955-A
Country	US
Kind code	B1
Filing date	Aug 19, 2014
Priority date	Aug 19, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A system includes a first plurality of processors, a second plurality of processors dissimilar from the first plurality of processors, a first arbitration device coupled to the first plurality of processors, and a second arbitration device coupled to the second plurality of processors. The first arbitration device and the second arbitration device is configured to receive event data, store the received event data, and to output the received event data at substantially a same time. At least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.

First claim

We claim:

1. A system comprising:
a first plurality of processors;
a second plurality of processors dissimilar from the first plurality of processors;
a first arbitration device coupled to the first plurality of processors; and
a second arbitration device coupled to the second plurality of processors, the first arbitration device and the second arbitration device being configured to receive event data, store the received event data, and to output the received event data at substantially a same time, wherein at least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.

2. The system of claim 1 , wherein the event data output from the first arbitration device is accessed by only one processor of the first plurality of processors.

3. The system of claim 1 , wherein the event data output from the second arbitration device is accessed by only one processor of the second plurality of processors.

4. The system of claim 1 , wherein at least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data output from the respective first arbitration device and the second arbitration device.

5. The system of claim 4 , wherein a processor of the first plurality of processors and a corresponding processor of the second plurality of processors are configured to access the same event data output from the respective first arbitration device and the second arbitration device.

6. The system of claim 1 , wherein the first plurality of processors and the second plurality of processors have an equal number of processors.

7. The system of claim 1 , wherein the first plurality of processors and the second plurality of processors have a differing number of processors.

8. The system of claim 1 , wherein the first arbitration device and the second arbitration device are configured to synchronize the received event data with each other.

9. The system of claim 1 , wherein the received event data is stored at substantially the same time in the first arbitration device and the second arbitration device.

10. The system of claim 1 , wherein the first plurality of processors and the second plurality of processors are configured to access the event data output from the respective first arbitration device and the second arbitration device in response to a synchronization signal.

11. The system of claim 10 , wherein a time at which an event data is accessed by a processor of the first plurality of processors is different than a time at which an event data is accessed by a corresponding processor of the second plurality of processors.

12. A system comprising:
a first plurality of processors;
a second plurality of processors dissimilar from the first plurality of processors;
a first arbitration device coupled to the first plurality of processors; and
a second arbitration device coupled to the second plurality of processors, the first arbitration device configured to synchronize computation data output from at least one processor of the first plurality of processors and the second arbitration device configured to synchronize computation data output from at least one processor of the second plurality of processors, the computation data being synchronized such that the computation data are output at substantially a same time.

13. The system of claim 12 , wherein the respective computation data are output by only one processor of the first plurality of processors and only one processor of the second plurality of processors.

14. The system of claim 12 , wherein at least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to produce computation data.

15. The system of claim 14 , wherein corresponding processors of the first plurality of processors and the second plurality of processors are configured to produce the computation data.

16. The system of claim 12 , wherein the first plurality of processors and the second plurality of processors are configured to produce outputs in response to a synchronization signal, the outputs being produced independent of each other, and the synchronization signal indicating an end of a time period for computing the outputs.

17. A method for synchronizing access of event data in a computing device of a flight control system, the method comprising:
receiving event data in a first arbitration device;
receiving the event data in a second arbitration device at substantially a same time as receiving the event data in the first arbitration device;
storing the event data in the first arbitration device and the second arbitration device;
outputting the event data at substantially a same time from the first arbitration device and the second arbitration device;
accessing the event data output from the first arbitration device by at least one processor of a first plurality of processors; and
accessing the event data output from the second arbitration device by at least one processor of a second plurality of processors dissimilar from the first plurality of processors, the event data being accessed at substantially a same time from the first arbitration device and the second arbitration device.

18. The method of claim 17 , further comprising:
accessing the event data output from the first arbitration device by only one processor of the first plurality of processors; and
accessing the event data output from the second arbitration device by only one processor of the second plurality of processors.

19. The method of claim 17 , further comprising:
accessing the event data output from the first arbitration device by at least one processor of the first plurality of processors; and
accessing the event data output from the second arbitration device by at least one processor of the second plurality of processors.

20. The method of claim 19 , wherein a processor of the first plurality of processors and a corresponding processor of the second plurality of processors are configured to access the same event data output at the respective first arbitration device and second arbitration device.

Assignees

• Kovalan Mark A
• Singer Mark Clifford
• Bader Douglas L
• Johnson Douglas Robert
• Roltgen Iii John William
• Rockwell Collins Inc

Inventors

• Kovalan Mark A
• Singer Mark Clifford
• Bader Douglas L
• Johnson Douglas Robert
• Roltgen Iii John William

Classifications

• G06F2213/3604

  Coding information on multiple lines · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• G06F2213/0064

  Latency reduction in handling transfers · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title