On-chip combined hot carrier injection and bias temperature instability monitor
US-2016377672-A1 · Dec 29, 2016 · US
US9612276B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9612276-B2 |
| Application number | US-201414299058-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 9, 2014 |
| Priority date | Aug 21, 2013 |
| Publication date | Apr 4, 2017 |
| Grant date | Apr 4, 2017 |
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A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode.
Opening claim text (preview).
What is claimed is: 1. A test device comprising: a test unit configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad; and a voltage selection circuit configured to apply a selection voltage to a ground pad of the semiconductor device under test, the selection voltage being selected among a plurality of voltages according to a test mode, wherein the voltage selection circuit is further configured to select a first voltage having a first voltage level greater than a ground voltage as the selection voltage in an open/short test mode and select the ground voltage as the selection voltage in a test mode other than the open/short test mode. 2. The test device of claim 1 , wherein when the selection voltage is the first voltage and a connectivity of the test pad is normal, the detected voltage at the test pad has a second voltage level less than the first voltage level. 3. The test device of claim 1 , wherein the test unit includes: a control unit configured to provide the test current in the open/short test mode; and a test interface chip configured to apply the test current to the test pad bypassing the test current through a test switch that is turned on in the open/short test mode. 4. The test device of claim 3 , wherein the voltage selection circuit includes: a selection voltage switch configured to select either the ground voltage or the first voltage in response to a control signal that is activated in the open/short test mode. 5. The test device of claim 4 , wherein the voltage selection circuit is located inside the test interface chip, and wherein the selection voltage switch receives the control signal from a controller included in the test interface chip. 6. The test device of claim 4 , wherein the voltage selection circuit is located outside the test interface chip, and wherein the selection voltage switch receives the control signal from the control unit. 7. The test device of claim 3 , wherein the voltage selection circuit is located outside the test interface chip, and wherein the voltage selection circuit receives the first voltage from the control unit. 8. A test system comprising: a semiconductor device under test including a test pad and a ground voltage pad, the semiconductor device under test being connected to provide a test response voltage at the test pad based on a test current and a selection voltage; a test unit including a current source, the test unit connected to detect the test response voltage at the test pad of the semiconductor device by applying the test current from the current source to the test pad; and a voltage selection circuit connected to apply the selection voltage to the ground voltage pad of the semiconductor device, the selection voltage being selected among a plurality of voltages according to a test mode. 9. The test system of claim 8 , wherein the semiconductor device includes: a first diode including a cathode connected to a power supply voltage and an anode connected to the test pad; and a second diode including a cathode connected to the test pad and an anode connected to the ground voltage pad, wherein in an open/short test mode, the test current is additionally provided to the test pad through the second diode. 10. The test system of claim 9 , wherein the power supply voltage is higher than a turn-on voltage of the second diode. 11. The test system of claim 10 , wherein the semiconductor device is configured such that a connectivity of the second diode is tested based on the test response voltage in the open/short test mode. 12. The test system of claim 11 , wherein the semiconductor device is configured such that the second diode is determined to be connected when the test response voltage corresponds to the difference value between the power supply voltage and the turn-on voltage of the second diode. 13. The test system of claim 11 , wherein the semiconductor device is configured such that the second diode is determined to be not connected when the absolute value of the test response voltage corresponds to the turn-on voltage of the second diode. 14. The test system of claim 11 , wherein the semiconductor device is configured such that the connectivity of the second diode and a connectivity of a diode of an interface chip of the test unit are determined to be not connected when the test response voltage is negatively infinite, the interface chip being connected to the test pad. 15. A method of testing a semiconductor device, the method comprising: preparing a test equipment and the semiconductor device to be tested; connecting the test equipment to a test pad and a ground pad of the semiconductor device; applying a first voltage to the ground pad when the semiconductor device is in an open/short test mode, the first voltage having a voltage level greater than a ground level; and measuring a voltage at the test pad and determining whether a connectivity of the test pad is normal or abnormal. 16. The method of claim 15 , further comprising: applying a first test current to the test pad, wherein applying the first voltage to the ground pad includes applying a second test current to the test pad through a diode connected between the test pad and the ground pad. 17. The method of claim 16 , wherein a level of the first voltage is greater than a turn-on voltage of the diode. 18. The method of claim 16 , wherein a voltage level of the test pad is VDD-VD when a connectivity of the test pad is normal, the first voltage being VDD and the turn-on voltage of the diode being VD. 19. The method of claim 15 , further comprising: applying a ground voltage to the ground pad when the semiconductor device is in a test mode other than the open/short test mode.
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