Method for performing phase shift control for timing recovery in an electronic device, and associated apparatus

Patent metadata

Field	Value
Publication number	US-9608798-B2
Application number	US-201615194509-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Jun 2, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.

First claim

What is claimed is:

1. A method for performing phase shift control for timing recovery in an electronic device, the method comprising:
generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and
performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal, wherein the reproduced data are reproduced at a data bus of the receiver, and the set of digital control signals is generated according to feedback signals from the data bus.

2. The method of claim 1 , further comprising:
utilizing a digital low pass filter to perform digital low pass filtering on derivatives of the feedback signals to generate the set of digital control signals.

3. The method of claim 2 , further comprising:
utilizing a phase detector to perform phase detection on the feedback signals from the data bus of the receiver to generate phase detection results, wherein the derivatives of the feedback signals comprise the phase detection results.

4. The method of claim 1 , wherein the oscillator comprises a plurality of stages; and the phase shift of the output signal of the oscillator is controlled by selectively combining the set of clock signals into a specific stage of the plurality of stages according to the set of digital control signals.

5. The method of claim 4 , wherein the phase shift of the output signal of the oscillator is controlled by injecting at least one portion of the set of clock signals into the specific stage according to the set of digital control signals, wherein a signal count of the at least one portion of the set of clock signals corresponds to the set of digital weightings carried by the set of digital control signals.

6. The method of claim 4 , wherein the phase shift of the output signal of the oscillator is controlled by selectively combining the set of clock signals into the specific stage of the plurality of stages according to the set of digital control signals and by selectively combining another set of clock signals into another stage of the plurality of stages according to another set of digital control signals.

7. The method of claim 6 , wherein the phase shift of the output signal of the oscillator is controlled by injecting at least one portion of the set of clock signals into the specific stage of the plurality of stages according to the set of digital control signals and by injecting at least one portion of the other set of clock signals into the other stage of the plurality of stages according to the other set of digital control signals, wherein a signal count of the at least one portion of the set of clock signals corresponds to the set of digital weightings carried by the set of digital control signals, and a signal count of the at least one portion of the other set of clock signals corresponds to a set of digital weightings carried by the other set of digital control signals.

8. The method of claim 6 , wherein the other set of clock signals is equivalent to the set of clock signals.

9. The method of claim 4 , wherein each stage of the plurality of stages comprises a voltage mode amplifier.

10. The method of claim 4 , wherein each stage of the plurality of stages comprises a current mode amplifier.

11. An apparatus for performing phase shift control for timing recovery in an electronic device, the apparatus comprising at least one portion of the electronic device, the apparatus comprising:
an oscillator arranged to generate an output signal;
at least one mixing circuit, electrically connected to the oscillator, arranged to perform phase shift control on the output signal of the oscillator, wherein the at least one mixing circuit comprises a set of clock receiving terminals arranged to obtain a set of clock signals, and the at least one mixing circuit controls a phase shift of the output signal of the oscillator by selectively combining the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals;
a clock generator, arranged to generate the set of clock signals; and
a sampling circuit, positioned in a receiver in the electronic device, arranged to perform timing recovery and sampling on a receiver input signal of the receive according to the output signal of the oscillator to reproduce data from the receiver input signal, wherein the reproduced data are reproduced at a data bus of the receiver, and the set of digital control signals is generated according to feedback signals from the data bus.

12. The apparatus of claim 11 , further comprising:
a digital low pass filter arranged to perform digital low pass filtering on derivatives of the feedback signals to generate the set of digital control signals.

13. The apparatus of claim 12 , further comprising:
a phase detector arranged to perform phase detection on the feedback signals from the data bus of the receiver to generate phase detection results, wherein the derivatives of the feedback signals comprise the phase detection results.

14. The apparatus of claim 11 , wherein the oscillator comprises a plurality of stages; and the at least one mixing circuit controls the phase shift of the output signal of the oscillator by selectively combining the set of clock signals into a specific stage of the plurality of stages according to the set of digital control signals.

15. The apparatus of claim 14 , wherein the at least one mixing circuit controls the phase shift of the output signal of the oscillator by injecting at least one portion of the set of clock signals into the specific stage according to the set of digital control signals, wherein a signal count of the at least one portion of the set of clock signals corresponds to the set of digital weightings carried by the set of digital control signals.

16. The apparatus of claim 14 , wherein the at least one mixing circuit further comprises:
another set of clock receiving terminals arranged to obtain another set of clock signals;
wherein the at least one mixing circuit controls the phase shift of the output signal of the oscillator by selectively combining the set of clock signals into the specific stage of the plurality of stages according to the set of digital control signals and by selectively combining the other set of clock signals into another stage of the plurality of stages according to another set of digital control signals.

17. The apparatus of claim 16 , wherein the at least one mixing circuit controls the phase shift of the output signal of the oscillator by injecting at least one portion of the set of clock signals into the specific stage of the plurality of stages according to the set of digital control signals and by injecting at least one portion of the other set of clock signals into the other stage of the plurality of stages according to the other set of digital control signals, wherein a signal count of the at least one portion of the set of clock signals corr

Assignees

• Mediatek Inc

Inventors

• Luo Yan-Bin
• Chen Bo-Jiun
• Wu Ke-Chung
• Huang Yi-Chieh

Classifications

• H03K2005/00052

  by mixing the outputs of fixed delayed signals with each other or with the input signal · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title