Semiconductor memory device, a memory module including the same, and a memory system including the same

Patent metadata

Field	Value
Publication number	US-9608631-B2
Application number	US-201514723614-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	May 29, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.”

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage; and
an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage”.

2. The semiconductor memory device of claim 1 , wherein a ratio between the power supply voltage and the VOH is determined according to a resistance of an on-die termination (ODT) resistor of a memory controller which receives the data signal.

3. The semiconductor memory device of claim 1 , wherein the output driver is a low voltage swing terminated logic (LVSTL) output driver.

4. The semiconductor memory device of claim 1 , wherein the ZQ calibration unit comprises:
a first calibration unit configured to generate the pull-up VOH code, which determines a current generated by a pull-up driver of the output driver, based on the first target VOH; and
a second calibration unit configured to generate a pull-down VOH code, which determines a resistance of a pull-down driver of the output driver, based on a second target VOH.

5. The semiconductor memory device of claim 4 , wherein the first calibration unit comprises:
a pull-up VOH control block configured to generate the first target VOH;
a first comparator configured to output a first comparison result obtained by comparing the first target VOH with a voltage at a first node;
a first code generator configured to generate the pull-up VOH code based on the first comparison result;
a replica pull-up driver configured to generate a first current at the first node based on the pull-up VOH code; and
a replica on-die termination (ODT) resistor configured to determine the voltage at the first node according to the first current.

6. The semiconductor memory device of claim 5 , wherein the pull-up VOH control block comprises:
a plurality of voltage dividers configured to respectively generate a divided power supply voltage; and
a selection circuit configured to select one of the divided power supply voltages as the first target VOH according to a mode register set (MRS) signal.

7. The semiconductor memory device of claim 5 , wherein a resistance of the replica ODT resistor is substantially the same as a resistance of an ODT resistor of a memory controller.

8. The semiconductor memory device of claim 4 , further comprising a pre-driver configured to generate a pull-up operating signal and a pull-down operating signal based on the pull-up VOH code, the pull-down VOH code, and internal data,
wherein the output driver comprises the pull-up driver which generates the current determined according to the pull-up operating signal and the pull-down driver which has the resistance determined according to the pull-down operating signal.

9. The semiconductor memory device of claim 1 , wherein a value obtained by dividing the power supply voltage by the VOH is 2.5 or 3.

10. A memory module, comprising:
at least one semiconductor memory device which comprises an output driver configured to generate a data signal having an output high-level voltage (VOH) proportional to a power supply voltage.

11. The memory module of claim 10 , wherein a ratio between the power supply voltage and the VOH is determined according to a resistance of an on-die termination (ODT) resistor of a memory controller which receives the data signal.

12. The memory module of claim 10 , wherein the semiconductor memory device further comprises a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to the power supply voltage and the VOH of the data signal is determined according to the pull-up VOH code.

13. The memory module of claim 12 , wherein the ZQ calibration unit comprises:
a first calibration unit configured to generate the pull-up VOH code, which determines a current generated by a pull-up driver of the output driver, based on the first target VOH; and
a second calibration unit configured to generate a pull-down VOH code, which determines a resistance of a pull-down driver of the output driver, based on a second target VOH.

14. The memory module of claim 13 , wherein the first calibration unit comprises:
a pull-up VOH control block configured to generate the first target VOH;
a first comparator configured to output a first comparison result obtained by comparing the first target VOH with a voltage at a first node;
a first code generator configured to generate the pull-up VOH code based on the first comparison result;
a replica pull-up driver configured to generate a first current at the first node based on the pull-up VOH code; and
a replica on-die termination (ODT) resistor configured to determine the voltage at the first node according to the first current.

15. The memory module of claim 14 , wherein the pull-up VOH control block comprises:
a plurality of voltage dividers configured to respectively generate a divided power supply voltage; and
a selection circuit configured to select one of the divided power supply voltages as the first target VOH according to a mode register set (MRS) signal.

16. The memory module of claim 14 , wherein a resistance of the replica ODT resistor is substantially the same as a resistance of an ODT resistor of a memory controller.

17. The memory module of claim 13 , wherein the semiconductor memory device further comprises a pre-driver configured to generate a pull-up operating signal and a pull-down operating signal based on the pull-up VOH code, the pull-down VOH code, and internal data, and
wherein the output driver comprises the pull-up driver which generates the current determined according to the pull-up operating signal and the pull-down driver which has the resistance determined according to the pull-down operating signal.

18. The memory module of claim 10 , wherein a value obtained by dividing the power supply voltage by the VOH is 2.5 or 3.

19. A memory system, comprising:
a memory module that includes at least one semiconductor memory device; and
a memory controller configured to receive a data signal from the semiconductor memory device,
wherein the semiconductor memory device comprises an output driver configured to generate the data signal having an output high-level voltage (VOH) proportional to a power supply voltage.

20. The memory system of claim 19 , wherein a ratio between the power supply voltage and the VOH is determined according to a resistance of an on-die termination (ODT) resistor of the memory controller.

21. A semiconductor memory device, comprising:
a ZQ calibration circuit configured to generate an output high level voltage (VOH) code according to a control code; and
an output driver configured to generate a data signal having a VOH calibrated in proportion to a power supply voltage according to the VOH code.

22. The semiconductor memory device of claim 21 wherein the control code is generated in response to a mode register set (MRS) signal.

23. The semiconductor memory device of claim 22 , wherein the MRS signal includes impedance information of an on-die termination (ODT) resistor of a memory controller.

24. The semiconductor memory device of claim 21 , wherein the VOH code includes a pull-up VOH code or a pull-down VOH code.

25. The semiconductor memory device of claim 21 , w

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ki Won
• Bae Seung Jun
• Park Joon Young
• Bae Yong Cheol

Classifications

• G11C29/50008

  of impedance · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C2207/2254

  Calibration · CPC title