Methods and apparatus to improve transient response performance of buck regulators
US-2024405676-A1 · Dec 5, 2024 · US
US9608626B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9608626-B1 |
| Application number | US-201514862744-A |
| Country | US |
| Kind code | B1 |
| Filing date | Sep 23, 2015 |
| Priority date | Sep 27, 2012 |
| Publication date | Mar 28, 2017 |
| Grant date | Mar 28, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (×M1) and the second MOSFET is characterized by a second multiplier (×M2) where a ratio of ×M2 to ×M1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit with precision current source comprising: a first metal-oxide semiconductor field-effect transistor (MOSFET) formed on a semiconductor substrate and having a first source, a first drain, and a first gate, wherein the first MOSFET is characterized by a first multiplier (×M1); a second MOSFET formed on the semiconductor substrate and having a second source, a second drain, and a second gate, wherein the second MOSFET is characterized by a second multiplier (×M2), and wherein a ratio of ×M2 to ×M1 is greater than one; an operational amplifier (op-amp) formed on the semiconductor substrate having a plus input, a minus input and an output, wherein the output of the op-amp is coupled to the first gate; a first resistor coupling the first gate to the second gate; a first current source coupling the plus input of the op-amp to a positive voltage supply; a second current source coupling the gate of the second MOSFET to ground; and a negative feedback circuit coupled to the second gate to limit an output current flowing through the second MOSFET. 2. An integrated circuit with precision current source as recited in claim 1 wherein the negative feedback circuit further comprises a third MOSFET formed on the semiconductor substrate and having a third source, a third drain, and a third gate, wherein the third MOSFET is characterized by a third multiplier (a1/Mn). 3. An integrated circuit with precision current source as recited in claim 2 wherein the second gate is coupled to the third gate. 4. An integrated circuit with precision current source as recited in claim 3 wherein the negative feedback circuit further comprises a fourth MOSFET formed on the semiconductor substrate and having a fourth source, a fourth drain, and a fourth gate. 5. An integrated circuit with precision current source as recited in claim 4 wherein the fourth drain is coupled to the second gate and third gate. 6. An integrated circuit with precision current source as recited in claim 5 wherein the negative feedback circuit further comprises a third current source coupling the fourth gate to ground. 7. An integrated circuit with precision current source as recited in claim 6 further comprising a fifth MOSFET having a fifth source, a fifth drain and a fifth gate, wherein the fifth drain is coupled to the fifth gate, the fifth source is coupled to the positive voltage supply, and the fifth drain is coupled to the third drain. 8. An integrated circuit with precision current source as recited in claim 7 further comprising a sixth MOSFET having a sixth source, a sixth drain and a sixth gate, wherein the sixth source is coupled to the positive voltage supply and the six drain is coupled to the fourth gate and the third current source. 9. An integrated circuit with precision current source as recited in claim 8 wherein the fifth gate is coupled to the sixth gate, whereby the fifth MOSFET and the sixth MOSFET comprise a current mirror. 10. An integrated circuit with precision current source as recited in claim 9 wherein the first MOSFET, the second MOSFET, the third MOSFET and the fourth MOSFET are NMOS transistors. 11. An integrated circuit with precision current source as recited in claim 10 wherein the fifth MOSFET and the sixth MOSFET are PMOS transistors. 12. An integrated circuit with precision current source comprising: a first metal-oxide semiconductor field-effect transistor (MOSFET) formed on a semiconductor substrate and having a first source, a first drain, and a first gate, wherein the first MOSFET is characterized by a first multiplier (×M1); a second MOSFET formed on the semiconductor substrate and having a second source, a second drain, and a second gate, wherein the second MOSFET is characterized by a second multiplier (×M2), and wherein a ratio of ×M2 to ×M1 is greater than one; an operational amplifier (op-amp) formed on the semiconductor substrate having a plus input, a minus input and an output, wherein the output of the op-amp is coupled to the first gate; first current source coupled between a voltage source and the plus input of the op-amp; second current source coupling the second gate of the second MOSFET to ground; and a first resistor coupling the first gate to the second gate. 13. An integrated circuit with precision current source as recited in claim 12 wherein the first MOSFET has a first width (W1) and a first length (L1), and wherein the second MOSFET has a second width (W2) and a second length (L2). 14. An integrated circuit with precision current source as recited in claim 13 wherein L1 is approximately equal to L2. 15. An integrated circuit with precision current source as recited in claim 14 wherein W2 is greater than W1. 16. An integrated circuit with precision current source as recited in claim 15 wherein the first MOSFET and the second MOSFET are both n-channel metal-oxide semiconductor (NMOS) transistors and wherein the first drain and the second drain are electrically connected to an output node and the second source is electrically connected to ground. 17. An integrated circuit with precision current source as recited in claim 16 further comprising a second resistor coupling the plus input to ground and a third resistor coupling the first source to ground. 18. An integrated circuit with precision current source as recited in claim 17 wherein the first source is coupled to the minus input. 19. An integrated circuit with precision current source as recited in claim 18 wherein first MOSFET has a first gate-to-source voltage (Vgs1) and the second MOSFET has a second gate-to-source voltage (Vgs2), where Vgs1 is approximately equal to Vgs2. 20. An integrated circuit with precision current source as recited in claim 19 wherein voltage drops across the first resistor, the second resistor, and the third resistor are substantially equal.
the output circuit comprising more than one controlled field-effect transistor · CPC title
Voltage to current converters (amplifiers H03F) · CPC title
Linear regulators · CPC title
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.