Semiconductor structure with a doped region between two deep trench isolation structures

Patent metadata

Field	Value
Publication number	US-9608105-B2
Application number	US-201514730748-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Jul 17, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.

First claim

What is claimed is:

1. A transistor array comprising:
a semiconductor material having a first conductivity type;
a first and second transistor structures, each having:
a source formed in the semiconductor material, the source having a second conductivity type;
a drain formed in the semiconductor material, the drain being laterally spaced apart from the source, and having the second conductivity type; and
a shallow trench isolation structure formed in the semiconductor material, the shallow trench isolation structure touching the drain, the shallow trench isolation structure lies laterally between the source and the drain within each of the first and second transistor structures;

a deep isolation structure formed in the semiconductor material, the deep isolation structure laterally surrounding the source and the drain of each of the first transistor structure and the second transistor structure;
a trench isolation structure formed in the semiconductor material, the trench isolation structure having a depth that is substantially equal to a depth of the deep isolation structure, and laterally surrounding the deep isolation structure;
a region of the second conductivity type that touches and lies between the deep isolation structure and the trench isolation structure;
two or more first buried regions that touch the semiconductor material and lie below the two or more transistor structures, the two or more first buried regions each having the second conductivity type; and
a second buried region that touches the semiconductor material and the first buried regions and lies laterally between the first buried regions, the second buried region having the first conductivity type and a dopant concentration that is greater than a dopant concentration of the semiconductor material.

2. The transistor array of claim 1 wherein the deep isolation structure laterally surrounds the source and the drain of each transistor structure in the array.

3. The transistor array of claim 2 wherein each transistor structure further has a drain drift region formed in the semiconductor material, the drain drift region touching the drain and the deep isolation structure.

4. The transistor array of claim 3 wherein a bottom surface of the deep isolation structure touches a region having the first conductivity type.

5. The transistor array of claim 4 wherein each of the first and second transistor structures further has a double diffused well formed in the semiconductor material that lies between the source and the drain within each of the first and second transistor structures.

Assignees

• Texas Instruments Inc

Inventors

• Tamura Takehito
• Hu Binghua
• Pendharkar Sameer
• Mathur Guru

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L29/1083

  Electricity · mapped topic