Method of manufacturing thin-film transistor substrate

Patent metadata

Field	Value
Publication number	US-9608089-B2
Application number	US-201615056033-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Jul 9, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.

First claim

What is claimed is:

1. A method of manufacturing a thin-film transistor substrate, the method comprising:
forming a semiconductor pattern layer on a substrate;
forming a first insulating film on the semiconductor pattern layer;
forming, on the first insulating film, a metal pattern layer comprising a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode;
forming a cover layer covering the gate electrode, and removing the first and second alignment electrodes, wherein the cover layer is formed by forming a photoresist layer on the metal pattern layer, and then exposing and developing the photoresist layer by using a first mask having a first pattern, wherein a width of the first pattern is larger than a width of the cover layer;
performing a first doping process by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask;
removing the cover layer; and
performing a second doping process by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.

2. The method of claim 1 , wherein, in the performing of the first doping process, the semiconductor pattern layer comprises a first region, and second and third regions respectively disposed at two sides of the first region, and wherein the second and third regions are doped with the first impurity.

3. The method of claim 2 , wherein, in the performing of the second doping process, the first region of the semiconductor pattern layer comprises a fourth region corresponding to a center region of the first region, and fifth and sixth regions respectively disposed at two sides of the fourth region, wherein the fifth and sixth regions are doped with the second impurity, and the second and third regions are again doped with the second impurity.

4. The method of claim 3 , wherein the fourth region is formed at a location corresponding to the gate electrode and has substantially a same width as the gate electrode.

5. The method of claim 2 , wherein a width of the cover layer is substantially the same as a width of the first region.

6. The method of claim 1 , wherein the photoresist layer comprises a pre-cover layer having substantially a same width as the first pattern via exposure, and wherein while developing the photoresist layer, the width of the pre-cover layer is reduced to a width of the cover layer.

7. The method of claim 6 , wherein the pre-cover layer comprises first and second end regions respectively disposed at sides of the pre-cover layer, and wherein the first and second end regions are moved towards a center of the cover layer while developing the photoresist layer.

8. The method of claim 7 , wherein the amount of light incident on at least one of the first and second end regions of the pre-cover layer increases as a distance between the at least one of the first and second end regions and one of the first and second alignment electrodes, which is adjacent to the at least one of the first and second end regions, decreases.

9. The method of claim 8 , wherein a moving distance of the at least one of the first and second end regions increases as the distance between the at least one of the first and second end regions and one of the first and second alignment electrodes, which is adjacent to the at least one of the first and second end regions, decreases.

10. The method of claim 1 , wherein the photoresist layer comprises a positive type photoresist.

11. The method of claim 10 , wherein the first pattern comprises a light blocker.

12. The method of claim 1 , wherein the first impurity and the second impurity are a same material.

13. The method of claim 1 , wherein the first and second alignment electrodes are removed via wet-etching.

14. The method of claim 1 , wherein a width of the metal pattern layer is smaller than a width of the semiconductor pattern layer.

15. The method of claim 1 , wherein the first and second alignment electrodes are respectively spaced apart from the two sides of the gate electrode at an equal distance.

16. A method of manufacturing a thin-film transistor substrate, the method comprising:
forming a semiconductor pattern layer on a substrate;
forming a first insulating film on the semiconductor pattern layer;
forming a metal pattern layer comprising a gate electrode on the first insulating film;
forming a photoresist layer on the metal pattern layer;
exposing and developing the photoresist layer to form a cover layer, wherein the exposing is performed using a mask having a mask pattern, and wherein the mask pattern is wider than a width of the cover layer;
performing a first doping process by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask;
removing the cover layer; and
performing a second doping process by doping the semiconductor pattern layer with a second impurity using the gate electrode as a mask.

17. The method of claim 16 , wherein the metal pattern layer further comprises first and second alignment electrodes, and wherein the first and second alignment electrodes are removed after forming the cover layer.

18. The method of claim 16 , wherein the second impurity has a lower concentration than the first impurity.

19. The method of claim 16 , wherein a width of the metal pattern layer is smaller than a width of the semiconductor pattern layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Jongyun
• Kim Waljun
• Kim Junghyun
• Ahn Kiwan

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P30/22

  using masks · CPC title

• H01L21/32134

  Electricity · mapped topic

• H01L29/66757 Primary

  Electricity · mapped topic