Methods for forming fins for metal oxide semiconductor device structures

Patent metadata

Field	Value
Publication number	US-9607987-B2
Application number	US-201113996468-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

First claim

What is claimed is:

1. A method of fabricating a device, comprising:
forming silicon fins on a substrate;
forming a first dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of the silicon fins are exposed;
epitaxially growing a germanium layer on the upper region of the silicon fins;
depositing a second dielectric layer on the substrate; and
recessing the second dielectric layer to expose an upper surface of the silicon fins.

2. The method of claim 1 , wherein forming the first dielectric layer on the substrate comprises:
depositing the first dielectric layer on the substrate;
recessing the first dielectric layer to expose the upper region of the silicon fins.

3. The method of claim 1 , further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the second dielectric layer and upper regions of the germanium layer.

4. The method of claim 1 , further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the second dielectric layer and upper regions of the germanium; and
depositing a third dielectric layer on the substrate.

5. The method of claim 1 , further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below lower regions of the germanium layer; and
depositing a third dielectric layer on the substrate.

6. A method of fabricating a device, comprising:
forming silicon fins on a substrate;
epitaxially growing a germanium or silicon germanium layer on the silicon fins;
depositing a first dielectric layer on the germanium or silicon germanium layer;
planarizing the first dielectric layer such that an upper surface of the silicon fins are exposed and an upper surface of the germanium or silicon germanium layer is exposed.

7. The method of claim 6 , further comprising:
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the first dielectric layer and upper regions of the germanium or silicon germanium layer.

8. The method of claim 6 , further comprising:
depositing a second dielectric layer on the substrate.

9. The method of claim 6 , wherein the germanium or silicon germanium layer comprises germanium fins or silicon germanium fins having a pitch that is approximately one half of a pitch of the silicon fins.

10. A method of fabricating a device, comprising:
forming silicon fins on a substrate;
forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper surface of the silicon fins are exposed;
selectively etching the exposed upper surface of the silicon fins to a recessed level below upper regions of the dielectric layer;
depositing a germanium layer on the exposed upper surface of the silicon fins; and
annealing the germanium layer to form crystalline germanium fins.

11. The method of claim 10 , further comprising:
selectively epitaxially growing a layer on the exposed upper surface of the silicon fins.

12. The method of claim 11 , further comprising:
planarizing upper regions of the layer and the dielectric layer.

13. The method of claim 12 , wherein the layer comprises germanium or silicon germanium.

14. A method of fabricating a device, comprising:
forming silicon fins on a substrate;
forming a first dielectric layer on the substrate and adjacent to the silicon fins such that an upper region including sidewalls and an upper surface of the silicon fins are exposed; and
epitaxially growing a germanium layer on an exposed portion of the sidewalls and the upper surface of the upper region of the silicon fins.

15. The method of claim 14 , wherein the silicon fins have a height of 30 to 50 nanometers.

16. The method of claim 14 , wherein the silicon fins have a width of 5 to 10 nanometers.

17. The method of claim 14 , wherein the silicon fins have a pitch of 50 to 100 nanometers between adjacent silicon fins.

Assignees

• Giles Martin D
• Ghani Tahir
• Intel Corp

Inventors

• Giles Martin D
• Ghani Tahir

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D30/611 Primary

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title