Method for establishing interconnects in packages using thin interposers

Patent metadata

Field	Value
Publication number	US-9607973-B1
Application number	US-201514946162-A
Country	US
Kind code	B1
Filing date	Nov 19, 2015
Priority date	Nov 19, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

First claim

What is claimed is:

1. A method for interconnecting a first semiconductor die and a second semiconductor die, the method comprising:
attaching a splice interposer to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer;
attaching the first semiconductor die to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die;
attaching the first semiconductor die to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor, wherein the height of the second plurality of pillars is greater than the height of the third plurality of pillars; and
attaching the second semiconductor die to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die;
wherein the first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

2. The method of claim 1 , wherein the second plurality of pillars are formed at a central portion of the bottom surface of the first semiconductor die and the third plurality of pillars are formed at a peripheral portion of the bottom surface of the first semiconductor die.

3. The method of claim 1 , wherein the first semiconductor die comprises at least one of a CPU and a GPU and the second semiconductor die comprises at least one of a HBM, an optical I/O and an additional CPU or GPU.

4. The method of claim 1 , wherein the attaching the first semiconductor die to the top surface of the substrate through the second plurality of pillars comprises contacting the bottom ends of the second plurality of pillars with the top surface of the substrate and applying a heat reflow process to the second plurality of pillars to bond the first semiconductor die to the top surface of the substrate.

5. The method of claim 1 , wherein the attaching the first semiconductor die to the top surface of the splice interposer through the third plurality of pillars comprises contacting the bottom ends of the third plurality of pillars with the top surface of the splice interposer and applying a heat reflow process to the third plurality of pillars to bond the first semiconductor die to the splice interposer.

6. The method of claim 1 , wherein the attaching the second semiconductor die to the top surface of the splice interposer through the fourth plurality of pillars comprises contacting the bottom ends of the fourth plurality of pillars with the top surface of the splice interposer and applying a heat reflow process to the fourth plurality of pillars to bond the second semiconductor die to the splice interposer.

7. The method of claim 1 , wherein the top surface of the substrate and the top surface of the splice interposer are planarized.

8. The method of claim 1 , wherein the first to fourth plurality of pillars comprise at least one stacked pillar formed on a corresponding surface of the first semiconductor die, the second semiconductor die or the splice interposer,
wherein the stacked pillar comprises a first conductor layer formed on the corresponding surface, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer and a second solder layer formed on the second conductor layer.

9. The method of claim 8 , wherein the first conductor layer and the second conductor layer are formed from Cu,
wherein the first solder layer has a melting temperature lower than the melting temperature of Cu, and
wherein the first solder layer has a solidification temperature lower than the solidification temperature of the second solder layer.

10. The method of claim 9 , wherein a first Ni layer is provided between the first conductor layer and the first solder layer and a second Ni layer is provided between the second conductor layer and the first solder layer,
wherein the first solder layer comprises a circumferential portion extending beyond the circumference of the first Ni layer and the second Ni layer, and
wherein, when viewed from a sectional perspective of the stacked pillar, the circumferential portion of the first solder layer is substantially half-spherical to at least partially cover a side surface of the first Ni layer and a side surface of the second Ni layer.

Assignees

• Globalfoundries Inc

Inventors

• Fasano Benjamin V
• Cranmer Michael S
• Indyk Richard F
• Cox Harry
• Sakuma Katsuyuki
• Perfecto Eric D

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07253

  changes in shapes · CPC title