Chip package

Patent metadata

Field	Value
Publication number	US-9607951-B2
Application number	US-201313958794-A
Country	US
Kind code	B2
Filing date	Aug 5, 2013
Priority date	Aug 5, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

According to an embodiment of the present invention, a chip package is provided. The chip package includes a substrate. A chip is disposed on the substrate. A stiffener is disposed on the substrate. The thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate.

First claim

What is claimed is:

1. A chip package, comprising:
a first substrate;
a chip disposed on the first substrate;
a stiffener disposed on the first substrate, wherein the stiffener has a thermal conductivity higher than that of the first substrate, the chip is exposed by an opening of the stiffener, and the stiffener is in direct physical contact with an outer side surface of the first substrate; and
a second substrate, wherein the second substrate is a printed circuit board, the first substrate and the chip are disposed on a surface of the second substrate, the stiffener extends on a conducting pad disposed on or in the second substrate, and the stiffener electrically connects with the conducting pad and has a shielding function to prevent signal interference.

2. The chip package as claimed in claim 1 , wherein the stiffener extends beyond an edge of the first substrate.

3. The chip package as claimed in claim 1 , wherein the stiffener extends on a top surface of the chip.

4. The chip package as claimed in claim 3 , further comprising a bonding layer disposed between the top surface of the chip and the stiffener.

5. The chip package as claimed in claim 1 , wherein the stiffener is in direct contact with the chip.

6. The chip package as claimed in claim 1 , further comprising a filling layer disposed on the first substrate and surrounding a portion of the chip.

7. The chip package as claimed in claim 6 , wherein the stiffener is in direct contact with the filling layer.

8. The chip package as claimed in claim 6 , wherein the stiffener is not in direct contact with the filling layer.

9. The chip package as claimed in claim 1 , further comprising a bonding layer disposed between the first substrate and the stiffener.

10. The chip package as claimed in claim 1 , further comprising a plurality of conducting elements disposed between the first substrate and the second substrate.

11. The chip package as claimed in claim 1 , wherein the conducting pad is a ground pad.

12. The chip package as claimed in claim 1 , further comprising a solder joint disposed between the conducting pad and the stiffener.

13. The chip package as claimed in claim 1 , wherein the stiffener comprises stainless steel, copper, aluminum, gold, silver, or combinations thereof.

14. The chip package as claimed in claim 1 , wherein the first substrate comprises an organic material.

15. The chip package as claimed in claim 1 , further comprising a plurality of conducting elements disposed between the chip and the first substrate.

16. The chip package as claimed in claim 1 , wherein the first substrate has a thickness smaller than that of the second substrate.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Ko Uming
• Lin Tzu-Hung
• Chen Tai-Yu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W76/40

  Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title