Copper bump joint structures with improved crack resistance

Patent metadata

Field	Value
Publication number	US-9607936-B2
Application number	US-61946809-A
Country	US
Kind code	B2
Filing date	Nov 16, 2009
Priority date	Oct 29, 2009
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a first work piece comprising:
a semiconductor substrate;
a copper bump over the semiconductor substrate;
a barrier layer over the copper bump; and
an alloy layer over the barrier layer, wherein the alloy layer comprises palladium and a metal selected from the group consisting essentially of copper, nickel, and combinations thereof;

a second work piece comprising a bond pad; and
a solder layer between and adjoining the first work piece and the second work piece, wherein the alloy layer is between the barrier layer and the solder layer, with opposite surfaces of the alloy layer contacting the barrier layer and the solder layer, wherein the solder layer electrically connects the copper bump to the bond pad, and the solder layer comprises palladium-rich grains distributed in the solder layer, and wherein the palladium-rich grains are distributed from a surface region of the solder layer to a center of the solder layer, and from the surface region to the center, palladium weight percentages reduce gradually.

2. The integrated circuit structure of claim 1 , wherein the palladium-rich grains have a palladium weight percentage between about 5 percent and about 10 percent.

3. The integrated circuit structure of claim 1 , wherein an average palladium weight percentage in the solder layer is about 0.15% to about 0.3% percent.

4. The integrated circuit structure of claim 1 , wherein the bond pad of the second work piece comprises copper.

5. The integrated circuit structure of claim 1 , wherein the palladium-rich grains have first palladium weight percentages, and wherein the palladium-rich grains are surrounded by solder region having palladium weight percentages lower than the first palladium weight percentages.

6. The integrated circuit structure of claim 1 , wherein the first work piece is a semiconductor chip comprising integrated circuits, and the second work piece is a package substrate.

7. The integrated circuit structure of claim 1 , wherein the first work piece is a package substrate, and the second work piece is a semiconductor chip comprising integrated circuits.

8. The integrated circuit structure of claim 1 , wherein the alloy layer comprises copper.

9. The integrated circuit structure of claim 1 , wherein the alloy layer comprises nickel.

10. The integrated circuit structure of claim 1 , wherein the second work piece comprises a palladium layer between the bond pad and the solder layer.

11. The integrated circuit structure of claim 10 , wherein the second work piece comprises a barrier layer between the bond pad and the palladium layer.

Assignees

• Hsiao Ching-Wen
• Wu Jiun Yi
• Huang Ru-Ying
• Chen Chen-Shien
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsiao Ching-Wen
• Wu Jiun Yi
• Huang Ru-Ying
• Chen Chen-Shien

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title