3-d structured two-phase cooling boilers with nano structured boiling enhancement coating
US-2024431075-A1 · Dec 26, 2024 · US
Power semiconductor module and method for cooling power semiconductor module
US9607924B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9607924-B2 |
| Application number | US-201514824871-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2015 |
| Priority date | Aug 14, 2014 |
| Publication date | Mar 28, 2017 |
| Grant date | Mar 28, 2017 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor module. The module comprises a power semiconductor device and an island of thermally conducting foam embedded into the printed circuit board. The power semiconductor device and the island of thermally conducting foam are positioned on top of each other, and the island is arranged to form a path for a flowing coolant cooling the power semiconductor device.
First claim
Opening claim text (preview).
The invention claimed is: 1. A power semiconductor module comprising a printed circuit board which comprises a power semiconductor device and an island of thermally conducting foam embedded in the printed circuit board, wherein the power semiconductor device and the island of thermally conducting foam are positioned on top of each other, and the island is arranged to form a path for a flowing coolant cooling the power semiconductor device, the foam comprises portions having different average pore sizes or bulk densities, and a portion of foam closest to the power semiconductor device has a higher average pore size in order to achieve a larger flow of coolant in the portion of foam closest to the power semiconductor device. 2. A power semiconductor module as claimed in claim 1 , wherein the foam comprises portions having different thermal conductivities. 3. A power semiconductor module as claimed in claim 1 , wherein the module comprises a plurality of islands of thermally conducting foam, wherein at least two islands are interconnected via a piece of piping so that the two islands and the piping form a path for a coolant to flow through. 4. A method for cooling a power semiconductor device embedded in a printed circuit board, wherein the method comprises embedding thermally conducting foam in the printed circuit board such that the power semiconductor device and the thermally conducting foam are positioned on top of each other, and that the foam forms an island that conducts a coolant cooling the power semiconductor device, wherein the foam comprises portions having different average pore sizes or bulk densities, wherein a portion of foam closest to the power semiconductor device has a higher average pore size in order to achieve a larger flow of coolant in the portion of foam closest to the power semiconductor device, and supplying coolant through the thermally conducting foam. 5. A power semiconductor module as claimed in claim 2 , wherein the module comprises a plurality of islands of thermally conducting foam, wherein at least two islands are interconnected via a piece of piping so that the two islands and the piping form a path for a coolant to flow through.
Assignees
Inventors
Classifications
by a substrate and the encapsulations · CPC title
the multiple chips being integrally enclosed · CPC title
comprising holes having chips therein · CPC title
Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title
of die-attach connectors · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9607924B2 cover?
- The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor module. The module comprises a power semiconductor device and an island of thermally conducting foam embedded into the printed circuit board. The power semiconductor device and the island of thermally conducting foam are positioned on top o…
- Who is the assignee on this patent?
- Abb Technology Oy
- What technology area does this patent fall under?
- Primary CPC classification H10W40/47. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).