Package on package interconnect structure

Patent metadata

Field	Value
Publication number	US-9607921-B2
Application number	US-201213349405-A
Country	US
Kind code	B2
Filing date	Jan 12, 2012
Priority date	Jan 12, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

First claim

What is claimed is:

1. A structure comprising:
a seed layer over a semiconductor substrate;
a post passivation interconnect layer formed over the semiconductor substrate and the seed layer, the post passivation interconnect layer contacting a top surface of the seed layer;
an immersion tin layer formed on the post passivation interconnect layer, the immersion tin layer contacting a top surface and sidewalls of the post passivation interconnect layer, the immersion tin layer contacting sidewalls of the seed layer;
a metal bump formed on the immersion tin layer;
a molding compound layer formed over the semiconductor substrate, wherein the immersion tin layer is embedded in the molding compound layer, wherein the immersion tin layer is directly contacting the molding compound layer, the molding compound layer comprising:
a lower portion, wherein a lower portion of the metal bump is embedded in the lower portion of the molding compound layer; and
a concave meniscus portion over the lower portion of the molding compound layer, wherein the concave meniscus portion surrounds a middle portion of sidewalls of the metal bump.

2. The structure of claim 1 , further comprising:
a first metal layer formed over the semiconductor substrate;
a first dielectric layer formed on the first metal layer;
a second metal layer formed on the first dielectric layer;
a first passivation layer formed over the second metal layer;
a second passivation layer formed over the first passivation layer;
a bond pad embedded in the first passivation layer and the second passivation layer, the bond pad having a lower portion having a first width and an upper portion having a second width greater than the first width, a bottom surface of the lower portion being co-planar with a bottom surface of the first passivation layer, the upper portion extending into the second passivation layer; and
a protection layer formed on the second passivation layer, the post passivation interconnect layer being over the protection layer and the bond pad, the seed layer contacting the bond pad through the protection layer.

3. The structure of claim 2 , wherein the bond pad is an aluminum bond pad.

4. The structure of claim 2 , wherein the protection layer is a polyimide layer.

5. The structure of claim 1 , wherein the metal bump is a solder ball.

6. The structure of claim 1 , wherein the metal bump comprises:
a bottom metal portion formed on the post passivation interconnect layer; and
an upper solder portion formed over the bottom metal portion.

7. The structure of claim 1 , further comprising a metal bump pad formed between the metal bump and the post passivation interconnect layer.

8. The structure of claim 1 , wherein the immersion tin layer is a continuous layer along the sidewalls of the seed layer and the sidewalls and the top surface of the post passivation interconnect layer, and wherein the immersion tin layer has a same thickness along its entire length.

9. A system comprising:
a packaging substrate having a plurality of bump pads; and
a semiconductor device coupled to the packaging substrate through a plurality of metal bumps, wherein the semiconductor device comprises:
a semiconductor substrate;
the plurality of metal bumps, each of which is in physical contact with an immersion tin layer on a corresponding interconnection pad, the immersion tin layers being on top surfaces and sidewalls of each of the interconnection pads, each of the interconnection pads having a seed layer interposed between the interconnection pads and the semiconductor substrate, the immersion tin layers contacting sidewalls of the seed layers, wherein the immersion tin layer is between each of the plurality of metal bumps and the corresponding interconnection pad, wherein the immersion tin layer is a continuous layer along the sidewalls of the seed layers and the sidewalls and the top surface of the interconnection pads, and wherein the immersion tin layer has a same thickness along its entire length; and
a molding compound layer formed over the semiconductor substrate, wherein the molding compound layer comprises a concave meniscus surface between two adjacent metal bumps, wherein a first angle is formed by the concave meniscus surface of the molding compound layer proximate a metal bump and a plane parallel to a major surface of the semiconductor substrate, the first angle being in a range from about 10 degrees to about 50 degrees.

10. The system of claim 9 , further comprising:
a first metal layer formed over the semiconductor substrate;
a first dielectric layer formed on the first metal layer;
a second metal layer formed on the first dielectric layer;
a first passivation layer formed over the second metal layer;
a second passivation layer formed over the first passivation layer;
a bond pad embedded in the first passivation layer and the second passivation layer, the bond pad extending through the first passivation layer and extending at least partially through the second passivation layer; and
a protection layer formed on the second passivation layer, the seed layer being on the protection layer and contacting the bond pad through the protection layer.

11. The system of claim 10 , wherein:
the bond pad is an aluminum bond pad; and
the protection layer is a polyimide layer.

12. The system of claim 9 , wherein the molding compound layer is of a thickness in a range between about 50 um and about 150 um.

13. The system of claim 9 , wherein a distance between the molding compound layer and the package substrate is in a range between about 5 um and 150 um.

14. The system of claim 9 , wherein the concave meniscus surface of the molding compound layer has a triangle shape in a cross section view.

15. A device comprising:
a first metal layer formed over a first substrate;
a first dielectric layer formed on the first metal layer;
a second metal layer formed on the first dielectric layer;
a first passivation layer formed over the second metal layer;
a second passivation layer formed over the first passivation layer;
a bond pad embedded in the first passivation layer and the second passivation layer, the bond pad having a first portion having a first width and a second portion over the first portion, the second portion having a second width, the second width being greater than the first width, the first portion extending through the first passivation layer, and the second portion extending into the second passivation layer; and
a protection layer formed on the second passivation layer;
a seed layer formed over the protection layer and the bond pad, the seed layer contacting the bond pad;
a post passivation interconnect (PPI) over the seed layer, the protection layer, and the bond pad, the post passivation interconnect contacting the seed layer, the seed layer being interposed between the protection layer and the PPI, the seed layer being interposed between the bond pad and the PPI;
an immersion tin layer contacting a top surface and sidewalls of the PPI, the immersion tin layer contacting sidewalls of the seed layer;
a conductive connector on a top surface of the immersion tin layer;
a molding compound over the top surface of the PPI and surrounding at least a portion of the conductive connector, the molding compound having a concave top surface adjoining and surrounding the conductive connector, the molding compound contacting the top surface and sidewalls of the immersion tin layer; and
a second substrate coupled to the first substrate through the conductive connector.

16. The device of claim 15 , wherein the conca

Assignees

• Lu Wen-Hsiung
• Wu Yi-Wen
• Lin Chih-Wei
• Lin Hsiu-Jen
• Cheng Ming-Da
• Liu Chung-Shi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wen-Hsiung
• Wu Yi-Wen
• Lin Chih-Wei
• Lin Hsiu-Jen
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title