Semiconductor device including h-BN insulating layer and its manufacturing method

Patent metadata

Field	Value
Publication number	US-9607824-B2
Application number	US-201514958644-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 4, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A semiconductor device includes a support substrate, an insulating layer provided on the support substrate, and a semiconductor element provided on the insulating layer. The insulating layer has a lower insulating layer consisting of amorphous boron nitride, and an upper insulating layer provided on the lower insulating layer and including amorphous boron nitride and an hexagonal system boron nitride (h-BN) particles.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a support substrate;
an insulating layer provided on said support substrate; and
a semiconductor element provided on said insulating layer,
wherein said insulating layer comprises:
a lower insulating layer consisting of amorphous boron nitride provided directly on an upper surface of said support substrate; and
an upper insulating layer provided on an entire surface of said lower insulating layer and including amorphous boron nitride and hexagonal system boron nitride particles in said amorphous boron nitride,

wherein grooves are provided on a surface of said upper insulating layer, and
wherein said grooves are grid-shaped.

2. A semiconductor device comprising:
a support substrate;
an insulating layer provided on said support substrate; and
a semiconductor element provided on said insulating layer,
wherein said insulating layer comprises:
a lower insulating layer consisting of amorphous boron nitride provided directly on an upper surface of said support substrate; and
an upper insulating layer provided on an entire surface of said lower insulating layer and including amorphous boron nitride and hexagonal system boron nitride particles in said amorphous boron nitride,

wherein grooves are provided on a surface of said upper insulating layer, and
wherein a depth D of said grooves satisfies:
T/2 <D<2T/3

where T is a thickness of said upper insulating layer.

Assignees

• Stanley Electric Co Ltd

Inventors

• Tanaka Kazufumi

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/6329 Primary

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/68

  Organic materials, e.g. photoresists · CPC title

• H10P14/6938 Primary

  the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

• H01L21/02266

  Electricity · mapped topic