Method and apparatus for calculating delay timing values for an integrated circuit design

Patent metadata

Field	Value
Publication number	US-9607117-B2
Application number	US-201314650319-A
Country	US
Kind code	B2
Filing date	Jan 8, 2013
Priority date	Jan 8, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

First claim

The invention claimed is:

1. A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design, the method comprising:
applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage; and
calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values;
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage; and
applying reduced N/PBTI compensation margins to the delay values for the identified at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage.

2. The method of claim 1 , wherein the method further comprises:
applying default N/PBTI compensation margins to delay values for elements within the at least one setup timing stage;
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage; and
reducing the default N/PBTI compensation margins applied to the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

3. The method of claim 1 , wherein the method further comprises:
applying default N/PBTI compensation margins to delay values for elements within the at least one setup timing stage;
calculating at least one delay timing value for the at least one setup timing stage based at least partly on the delay values to which the default N/PBTI compensation margins have been applied;
determining whether timing constraints have been met based on the at least one delay timing value calculated using the delay values to which the default N/PBTI compensation margins have been applied; and
if at least one timing constraint has not been met:
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage;
reducing the default N/PBTI compensation margins applied to delay values for the identified at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage; and
recalculating the at least one delay timing value for the at least one setup timing stage based at least partly on the delay values to which the reduced N/PBTI compensation margins have been applied.

4. The method of claim 1 ,
wherein the method comprises applying no N/PBTI compensation margin to the delay values for the identified equivalent elements within the parallel timing paths of the at least one setup timing stage.

5. The method of claim 1 ,
wherein the method comprises applying partially reduced N/PBTI compensation margins to the delay values for the identified partially equivalent elements within the parallel timing paths of the at least one setup timing stage.

6. A method of performing static timing analysis of at least a part of an integrated circuit design, the method comprising
calculating at least one delay timing value for at least one setup timing stage within the integrated circuit design in accordance with claim 1 .

7. An apparatus comprising at least one signal processing module arranged to calculate at least one delay timing value for at least one setup timing stage within an integrated circuit design, the at least one signal processing module being arranged to:
apply Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage;
calculate the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values;
identify at least partially equivalent elements within parallel timing paths of the at least one setup timing stage; and
apply reduced N/PBTI compensation margins to the delay values of the identified at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage.

8. The apparatus of claim 7 , wherein the at least one signal processing module is arranged to calculate at least one delay timing value for at least one setup timing stage within an integrated circuit design as part of performing static timing analysis of the at least one setup timing stage of the integrated circuit design.

9. An article of manufacture including at least one non-transitory, tangible machine readable storage medium containing instructions that, when executed by a machine, cause the machine to calculate at least one delay timing value for at least one setup timing stage within an integrated circuit design, the instructions comprising:
applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage; and
calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values;
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage; and
applying reduced N/PBTI compensation margins to the delay values for the identified at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage.

10. The article of claim 9 , wherein the instructions further comprise:
applying default N/PBTI compensation margins to delay values for elements within the at least one setup timing stage;
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage; and
reducing the default N/PBTI compensation margins applied to the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

11. The article of claim 9 , wherein the instructions further comprise:
applying default N/PBTI compensation margins to delay values for elements within the at least one setup timing stage;
calculating at least one delay timing value for the at least one setup timing stage based at least partly on the delay values to which the default N/PBTI compensation margins have been applied;
determining whether timing constraints have been met based on the at least one delay timing value calculated using the delay values to which the default N/PBTI compensation margins have been applied; and
if at least one timing constraint has not been met:
identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage;
reducing the default N/PBTI compensation margins applied to delay values for the identified at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage; and
recalculating the at least one delay timing value for the at least one setup timing stage based at least partly on the delay values to which the reduced N/PBTI compensation margins have been applied.

12. The article of claim 9 , wherein the instructions further comprise:
applying no N/PBTI compensation margin to the delay values for the identified equivalent elements within the parallel timing paths of the at least one setup timing stage.

13. The article of claim 9 , wherein the instructions further comprise:
applying partially reduced N/PBTI compensation margins to the delay values for the identified partially equivalent elements within the parallel timing paths of the at least one setup timing stage.

Assignees

• Berkovitz Asher
• Priel Michael
• Sofer Sergey
• Nxp Usa Inc

Inventors

• Berkovitz Asher
• Priel Michael
• Sofer Sergey

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/35

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title