CAN bus edge timing control for dominant-to-recessive transitions

Patent metadata

Field	Value
Publication number	US-9606948-B2
Application number	US-201314087879-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Dec 5, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

First claim

What is claimed is:

1. A method of bus edge-timing control suitable for use in a controller area network (CAN) including nodes communicating over a differential bus including differential (dominant) data bit signals with a differential voltage, and common-mode (recessive) data bit signals with a common-mode voltage, each with a transmission bit period, comprising:
transmitting transmit data (TxD) generated by a node including dominant and recessive data bit signals;
detecting a dominant-to-recessive data bit falling-edge transition in the transmit data (TxD); and
during the dominant-to-recessive falling-edge transition, performing a recessive nulling operation by adding at least one recessive nulling impedance based on the common-mode voltage in parallel with the differential bus starting at the time of the dominant-to-recessive data bit transition and extending for a selected recessive nulling time period in order to increase a rate of decay of the dominant-to-recessive falling-edge transition.

2. The method of bus edge-timing control of claim 1 , further comprising:
a light recessive nulling (LRN) mode of the recessive nulling operation in which the recessive nulling time period is less than the transmission bit period.

3. The method of bus edge-timing control of claim 1 , wherein, for a point-to-point or point-to-multipoint bus node topology with a single transmitting node, the recessive nulling operation comprises:
performing a heavy recessive nulling (HRN) mode in which the recessive nulling time period includes the entire transmission bit period; and
adding at least two recessive nulling impedances based on the common-mode voltage in parallel with the differential bus; and
decreasing the transmission bit period for the recessive bit.

4. The method of bus edge-timing control of claim 2 , the LRN mode of the recessive nulling operation further comprising:
selecting the recessive nulling time period associated with the LRN operation as a function of at least one of an expected bus impedance during a recessive bus state bus distributed parasitic capacitance, and bus loading associated with the dominant-to-recessive falling-edge transition.

5. The method of bus edge-timing control of claim 2 , the LRN mode of the recessive nulling operation further comprising:
decreasing the transmission bit period for the recessive bit.

6. The method of bus edge-timing control of claim 2 , further comprising:
a heavy recessive nulling (HRN) mode of the recessive nulling operation in which the recessive nulling time period includes the entire transmission bit period;
the LRN and HRN modes being performed on a selective mutually exclusive basis.

7. The method of bus edge-timing control of claim 6 , the HRN mode of the recessive nulling operation further comprising:
adding at least two recessive nulling impedances based on the common-mode voltage in parallel with the differential bus.

8. The method of bus edge-bit timing control of claim 7 , further comprising operating in a mixed mode including:
performing the recessive nulling operation in HRN mode on each recessive bit not subject to bus arbitration and not subject to bus contention caused by simultaneous transmission from two or more nodes; and
performing the recessive nulling operation in LRN mode on each recessive bit subject to bus arbitration or subject to bus contention caused by simultaneous transmission from two or more nodes.

9. An apparatus for use in a node of a controller area network (CAN) with a CAN bus, comprising:
a main CAN node physical layer (PHY) differential driver circuit to
drive the CAN bus to a dominant state with a differential voltage for a dominant TxD bit, and
drive the CAN bus to a recessive state with a common-mode voltage for a recessive TxD bit,
each dominant and recessive state with a transmission bit period; and

a recessive nulling fractional differential driver circuit output-coupled to the main CAN node PHY differential driver circuit, operable during a dominant-to-recessive data bit falling-edge transition to insert a recessive nulling impedance in parallel with a differential output of the main CAN node PHY driver across the CAN bus for a selected recessive nulling time period based on the common-mode voltage, during a recessive nulling time period.

10. The apparatus of claim 9 , wherein the main CAN PHY differential driver circuit further comprises:
a differential pre-driver;
a PMOS transistor gate-coupled to an in-phase output of the differential pre-driver, a drain terminal of the PMOS transistor communicatively coupled to a voltage HIGH rail (CANH) of the CAN bus;
a first diode coupled in series with a current path of the PMOS transistor, a cathode terminal of the first diode coupled to a source terminal of the PMOS transistor and an anode terminal of the first diode coupled to a positive supply voltage rail;
an NMOS transistor gate-coupled to an out-of-phase output of the differential pre-driver, a source terminal of the NMOS transistor communicatively coupled to a ground voltage rail; and
a second diode coupled in series with a current path of the NMOS transistor, a cathode terminal of the second diode coupled to a drain terminal of the NMOS transistor and an anode terminal of the second diode coupled to a voltage LOW rail (CANL) of the CAN bus.

11. The apparatus of claim 9 , the recessive nulling fractional differential driver circuit further comprising:
a differential pre-driver;
a PMOS transistor gate-coupled to an in-phase output of the differential pre-driver, a drain terminal of the PMOS transistor communicatively coupled to a voltage HIGH rail (CANH) of the CAN bus;
a first diode coupled in series with a current path of the PMOS transistor, a cathode terminal of the first diode coupled to a source terminal of the PMOS transistor and an anode terminal of the first diode coupled to a common-mode voltage source;
an NMOS transistor gate-coupled to an out-of-phase output of the differential pre-driver, a source terminal of the NMOS transistor communicatively coupled to the common-mode voltage source; and
a second diode coupled in series with a current path of the NMOS transistor, a cathode terminal of the second diode coupled to a drain terminal of the NMOS transistor and an anode terminal of the second diode coupled to a voltage LOW rail (CANL) of the CAN bus.

12. The apparatus of claim 9 , further comprising:
a first timing control logic circuit to control a first recessive nulling fractional differential driver circuit, including:
an OR gate with an output coupled to the first recessive nulling fractional differential driver circuit to drive the fractional differential driver circuit to a conductive state when the OR gate output is logic LOW, a negated first input of the OR gate coupled to a dominant LOW TxD input line to ensure that a dominant LOW state of the TxD signal holds an output of the first fractional differential driver circuit in an inactive high impedance state;
an AND gate with an output coupled to a non-negated second input of the OR gate, a negated first input of the AND gate coupled to an active-HIGH flexible data rate (FD) indicator signal line to drive the first fractional differential driver circuit to the conductive state when the FD indicator signal is active during recessive TxD bit times; and
a delay line coupled between the TxD input line and a second input of the AND gate to cause the first fractional differential driver circuit to be driven to the conductive state at a TxD dominant-to-recessive transition for the selected recessive nulling time period and then to be released to the high impedance state at the end of the se

Assignees

• Texas Instruments Inc

Inventors

• Monroe Scott Allen
• Stout David Wayne

Classifications

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/3625

  using a time dependent access · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title