Microprocessor-assisted auto-calibration of voltage regulators

Patent metadata

Field	Value
Publication number	US-9606595-B2
Application number	US-201113994065-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.

First claim

What is claimed is:

1. A method comprising:
executing, by a processor, a predefined test workload;
receiving at the processor a measurement by a voltage regulator that provides current, voltage, and power to the processor, the measurement indicating an amount of current drawn by the processor for execution of the predefined test workload as measured by the voltage regulator;
accessing a stored value indicating an expected current for execution of the predefined test workload by the processor;
calculating a calibration factor based on the measured current and the stored value; and
adjusting power operation of the processor based on the calibration factor.

2. The method of claim 1 , wherein executing the predefined test workload comprises:
executing the predefined test workload in response to instructions from a BIOS (basic input/output system).

3. The method of claim 1 , wherein the executing, accessing, calculating, and adjusting are performed at initialization of a system that includes the processor.

4. The method of claim 1 , wherein receiving the measurement comprises:
receiving at least one measurement made for a current lower than a thermal design current, and at least one measurement made for a current higher than the thermal design current.

5. The method of claim 1 , wherein calculating the calibration factor further comprises:
calculating a static offset.

6. The method of claim 1 , wherein calculating the calibration factor further comprises:
calculating a slope of a current-response line.

7. The method of claim 1 , wherein calculating the calibration factor further comprises:
calculating a second-order computation of a slope of a current-response line.

8. The method of claim 1 , wherein the executing the predefined test workload further comprises:
providing a memory access workload to a memory device coupled to the processor;
receiving at the processor a measurement by a voltage regulator that provides current, voltage, and power to the memory device, the measurement indicating an amount of current drawn by the memory device for execution of the predefined test workload as measured by the voltage regulator;
accessing a stored value indicating an expected current for execution of the predefined test workload by the memory device; and
calculating a calibration factor based on the measured current and the stored value.

9. A method comprising:
receiving a calibration trigger by a processor, and, in response:
executing, by the processor, at least two predefined test workloads;
receiving, at the processor, at least two measurements by a reference power generator, the at least two measurements indicating an amount of current drawn by the processor for execution of each of the at least two predefined test workloads as measured by the power generator; and
storing the at least two measurements in the processor as expected currents for execution of the at least two predefined test workloads by the processor for a calculation of a calibration factor for dynamic runtime calibration.

10. The method of claim 9 , wherein storing the at least two measurements comprises:
setting a read-only memory (ROM) with values of the at least two measurements.

11. The method of claim 9 , wherein storing the at least two measurements comprises:
setting values of the at least two measurements into fuses on the processor.

12. The method of claim 9 , wherein storing the at least two measurements further comprises:
storing environment values to indicate voltage and temperature environments under which the at least two predefined test workloads were executed.

13. The method of claim 12 , wherein storing the environment values further comprises:
calculating scaling factors of the processor executing the at least two predefined test workloads based on temperature change.

14. The method of claim 12 , wherein storing the environment values further comprises:
calculating scaling factors of the processor executing the at least two predefined test workloads based on source voltage changes.

15. A processor comprising:
execution hardware to execute, during a boot sequence, a predefined test workload in response to a trigger to perform a dynamic calibration, the trigger to be generated by a basic input/output system (BIOS) coupled to the processor;
an input path to receive a measurement by a voltage regulator that provides power to the processor, the measurement indicating an amount of current drawn by the processor for execution of the predefined test workload as measured by the voltage regulator;
a storage device to store a value indicating an expected current for execution of the predefined test workload by the processor; and
a power control unit (PCU) to access the stored value and the measurement, calculate a calibration factor based on the measured current and the stored value, and adjust power operation of the processor based on the calculated calibration factor.

16. The processor of claim 15 , wherein the BIOS is to generate the trigger as part of a startup sequence.

17. The processor of claim 15 , wherein receiving the measurement comprises:
receiving at least one measurement made for a current lower than a thermal design current, and at least one measurement made for a current higher than the thermal design current.

18. The processor of claim 15 , wherein the PCU is to calculate the calibration factor including calculating a static offset.

19. The processor of claim 15 , wherein the PCU is to calculate the calibration factor including calculating a slope of a current-response.

20. The processor of claim 15 , wherein the PCU is to calculate the calibration factor including calculating a second-order computation of a slope of a current-response.

21. A system comprising:
a processor comprising:
execution hardware to execute a predefined test workload in response to a trigger to perform a dynamic calibration;
an input path to receive a measurement by a voltage regulator that provides power to the processor, the measurement indicating an amount of current drawn by the processor for execution of the predefined test workload as measured by the voltage regulator;
a storage device to store a value indicating an expected current for execution of the predefined test workload by the processor;
a power control unit (PCU) to access the stored value and the measurement, calculate a calibration factor based on the measured current and the stored value, and adjust power operation of the processor based on the calculated calibration factor; and

a hardware controller to manage a touchscreen interface device to receive input/output (I/O) to be processed by the processor.

22. The system of claim 21 , the input path receiving the measurement comprises:
receiving at least one measurement made for a current lower than a thermal design current, and at least one measurement made for a current higher than the thermal design current.

23. The system of claim 21 , wherein the PCU is to calculate the calibration factor including calculating a static offset.

24. The system of claim 21 , wherein the PCU is to calculate the calibration factor including calculating a slope of a current-response.

25. The system of claim 21 , wherein the PCU is to calculate the calibration factor including calculating a second-order computation of a slope of a current-response.

26. The system of claim 21 , further c

Assignees

• Varma Ankush
• Shrall Jeremy J
• Sistla Krishnakanth Venkata
• Ananthakrishnan Avinash N
• Garg Vivek
• Poirier Sr Christopher A
• Rowland Martin T
• Stanford Edward R
• Intel Corp

Inventors

• Varma Ankush
• Shrall Jeremy J
• Sistla Krishnakanth Venkata
• Ananthakrishnan Avinash N
• Garg Vivek
• Poirier Sr Christopher A
• Rowland Martin T
• Stanford Edward R

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title